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? 2007 microchip technology inc. ds39597c pic16f72 data sheet 28-pin, 8-bit cmos flash microcontoller with a/d converter downloaded from: http:///
ds39597c-page ii ? 2007 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mindi, miwi, mpasm, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powe rtool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona, gresham, oregon and mountain view, california. the companys quality system processes and procedures are for its pic ? mcus and dspic dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 1 pic16f72 device included: ?pic16f72 high performance risc cpu: ? only 35 single word instructions to learn ? all single cycle instructions except for program branches, which are two-cycle ? operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle ? 2k x 14 words of program memory, 128 x 8 bytes of data memory (ram) ? pinout compatible to pic16c72/72a and pic16f872 ? interrupt capability ? eight-level deep hardware stack ? direct, indirect and relative addressing modes peripheral features: ? high sink/source current: 25 ma ? timer0: 8-bit timer/counter with 8-bit prescaler ? timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock ? timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? capture, compare, pwm (ccp) module - capture is 16-bit, max. resolution is 12.5 ns - compare is 16-bit, max. resolution is 200 ns - pwm max. resolution is 10-bit ? 8-bit, 5-channel analog-to-digital converter ? synchronous serial port (ssp) with spi? (master/slave) and i 2 c? (slave) ? brown-out detection circuitry for brown-out reset (bor) cmos technology: ? low power, high speed cmos flash technology ? fully static design ? wide operating voltage range: 2.0v to 5.5v ? industrial temperature range ? low power consumption: - < 0.6 ma typical @ 3v, 4 mhz -20 a typical @ 3v, 32 khz -< 1 a typical standby current pin diagrams special microcontroller features: ? 1,000 erase/write cycle flash program memory typical ? power-on reset (por), power-up timer (pwrt) and oscillator start-up timer (ost) ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? programmable code protection ? power saving sleep mode ? selectable oscillator options ? in-circuit serial programming? (icsp?) via 2 pins ? processor read access to program memory mclr /v pp ra0/an0 ra1/an1 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/an4/ss v ss osc1/clki osc2/clko rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rb7/pgd rb6/pgc rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7rc6 rc5/sdo rc4/sdi/sda ? 12 3 4 5 6 7 8 9 10 11 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 pdip, soic, ssop qfn 23 4 5 6 1 7 ra2/an2 ra3/an3/v ref ra4/t0cki ra5/an4/ss v ss osc1/clki osc2/clko 15 16 17 18 19 20 21 rb3rb2 rb1 rb0/int v dd v ss rc7 rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6 232425 26 2728 22 ra1/an1 ra0/an0 mclr /v pp rb7/pgd rb6/pgc rb5 rb4 10 11 8 9 12 13 14 pic16f72 pic16f72 28-pin, 8-bit cmos flash mcu with a/d converter downloaded from: http:///
pic16f72 ds39597c-page 2 ? 2007 microchip technology inc. key reference manual features pic16f72 operating frequency dc - 20 mhz resets and (delays) por, bor, (pwrt, ost) flash program memory - (14-bit words, 1000 e/w cycles) 2k data memory - ram (8-bit bytes) 128 interrupts 8 i/o ports porta, portb, portc timers timer0, timer1, timer2 capture/compare/pwm modules 1 serial communications ssp 8-bit a/d converter 5 channels instruction set (no. of instructions) 35 downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 3 pic16f72 table of contents 1.0 device overview ....................................................... ...................................................... ............................................................. 5 2.0 memory organization .......................................... ................................................... ............ .......................................................... 7 3.0 i/o ports ......................................................................................... .......................... .................................................................. 21 4.0 reading program memory ........................................ ................................................... ........... ................................................... 27 5.0 timer0 module .............................................. ................................................... .............. ............................................................ 29 6.0 timer1 module .............................................. ................................................... .............. ............................................................ 31 7.0 timer2 module .............................................. ................................................... .............. ............................................................ 35 8.0 capture/compare/pwm (ccp) module ....................................... ................................................... .. ......................................... 37 9.0 synchronous serial port (ssp) module .................................. ................................................... ... ............................................. 43 10.0 analog-to-digital converter (a/d) module....................................... ............................................ ............................................... 53 11.0 special features of the cpu...................................................... .......................................... ...................................................... 59 12.0 instruction set summary ........................................................ ............................................ ........................................................ 73 13.0 development support............................................ ................................................... ......... ......................................................... 81 14.0 electrical characteristics ........................................................ ......................................... ........................................................... 87 15.0 dc and ac characteristics graphs and tables................................... ............................................. ....................................... 107 16.0 package marking information................................... ................................................... .......... ................................................... 117 appendix a: revision history ............................................ ................................................... .... ..................................................... 123 appendix b: conversion considerations............................................ ............................................... ............................................. 123 index ................................................. ................................................... ...................... ........................................................................ 125 on-line support............................................... ................................................... .............. ................................................................. 131 reader response ................................................. ................................................... ............ .............................................................. 132 product identification system ................................................. ........................................................................................................... 133 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data 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pic16f72 ds39597c-page 4 ? 2007 microchip technology inc. notes: downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 5 pic16f72 1.0 device overview this document contains device specific information for the operation of the pic16f72 device. additional infor- mation may be found in the pic? mid-range mcu reference manual (ds33023), which may be down- loaded from the microchip website. the reference manual should be considered a complementary docu- ment to this data sheet, and is highly recommended reading for a better understanding of the device archi- tecture and operation of the peripheral modules. the pic16f72 belongs to the mid-range family of the pic devices. a block diagram of the device is shown in figure 1-1. the program memory contains 2k words, which trans- late to 2048 instructions, since each 14-bit program memory word is the same width as each device instruction. the data memory (ram) contains 128 bytes. there are 22 i/o pins that are user configurable on a pin-to-pin basis. some pins are multiplexed with other device functions. these functions include: ? external interrupt ? change on portb interrupt ? timer0 clock input ? timer1 clock/oscillator ? capture/compare/pwm ? a/d converter ? spi/i 2 c table 1-1 details the pinout of the device with descriptions and details for each pin. figure 1-1: pic16f72 block diagram flash memory 2k x 14 13 data bus 8 14 program bus instruction reg program counter 8-level stack (13-bit) ram file registers 128 x 8 direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clki osc2/clko mclr v dd , v ss timer0 a/d synchronous serial port porta portc rc0/t1oso/t1cki rc1/t1osi rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6 rc7 8 8 brown-out reset note 1: higher order bits are from the status register. ccp1 timer1 timer2 ra4/t0cki ra5/an4/ss ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 8 3 program portb rb0/int rb1 rb2 rb3 rb4 rb5 rb6/pgc rb7/pgd downloaded from: http:///
pic16f72 ds39597c-page 6 ? 2007 microchip technology inc. table 1-1: pic16f72 pinout description pin name pdip, soic, ssop pin# mlf pin# i/o/p type buffer type description osc1/clki 9 6 i st/cmos (3) oscillator crystal input/external clock source input. osc2/clko 10 7 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, the osc2 pin outputs clko, which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 26 i/p st master clear (reset) input or programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 2 27 i/o ttl ra0 can also be analog input0. ra1/an1 3 28 i/o ttl ra1 can also be analog input1. ra2/an2 4 1 i/o ttl ra2 can also be analog input2. ra3/an3/v ref 5 2 i/o ttl ra3 can also be analog input3 or analog reference voltage. ra4/t0cki 6 3 i/o st ra4 can also be the clock input to the timer0 module. output is open drain type. ra5/an4/ss 7 4 i/o ttl ra5 can also be analog input4 or the slave select for the synchronous serial port. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-up on all inputs. rb0/int 21 18 i/o ttl/st (1) rb0 can also be the external interrupt pin. rb1 22 19 i/o ttl rb2 23 20 i/o ttl rb3 24 21 i/o ttl rb4 25 22 i/o ttl interrupt-on-change pin. rb5 26 23 i/o ttl interrupt-on-change pin. rb6/pgc 27 24 i/o ttl/st (2) interrupt-on-change pin. serial programming clock. rb7/pgd 28 25 i/o ttl/st (2) interrupt-on-change pin. serial programming data. portc is a bi-directional i/o port. rc0/t1oso/ t1cki 11 8 i/o st rc0 can also be the timer1 oscillator output or timer1 clock input. rc1/t1osi 12 9 i/o st rc1 can also be the timer1 oscillator input. rc2/ccp1 13 10 i/o st rc2 can also be the capture1 input/compare1 output/ pwm1 output. rc3/sck/scl 14 11 i/o st rc3 can also be the synchronous serial clock input/output for both spi and i 2 c modes. rc4/sdi/sda 15 12 i/o st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 16 13 i/o st rc5 can also be the spi data out (spi mode). rc6 17 14 i/o st rc7 18 15 i/o st v ss 8, 19 5, 16 p ground reference for logic and i/o pins. v dd 20 17 p positive supply for logic and i/o pins. legend: i = input o = output i/o = input/output p = power = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input w hen configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when confi gured in rc oscillator mode and a cmos input otherwise. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 7 pic16f72 2.0 memory organization there are two memory blocks in the pic16f72 device. these are the program memory and the data memory. each block has separate buses so that concurrent access can occur. program memory and data memory are explained in this section. program memory can be read internally by the user code (see section 7.0). the data memory can further be broken down into the general purpose ram and the special function registers (sfrs). the operation of the sfrs that control the core are described here. the sfrs used to control the peripheral modules are described in the section discussing each individual peripheral module. additional information on device memory may be found in the pic? mid-range reference manual, (ds33023). 2.1 program memory organization pic16f72 devices have a 13-bit program counter capa- ble of addressing a 8k x 14 program memory space. the address range for this program memory is 0000h - 07ffh. accessing a location above the physically implemented address will cause a wraparound. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 2-1: program memory map and stack 2.2 data memory organization the data memory is partitioned into multiple banks that contain the general purpose registers and the special function registers. bits rp1 (status<6>) and rp0 (status<5>) are the bank select bits. each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are general purpose registers, implemented as static ram. all implemented banks contain sfrs. some high use sfrs from one bank may be mirrored in another bank, for code reduction and quicker access (e.g., the status register is in banks 0 - 3). 2.2.1 general purpose register file the register file can be accessed either directly, or indi- rectly, through the file select register fsr (see section 2.5). pc<12:0> 13 0000h 0004h 0005h 07ffh 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, returnretfie, retlw 0800h user memory space rp1:rp0 bank 00 0 01 1 10 2 11 3 downloaded from: http:///
pic16f72 ds39597c-page 8 ? 2007 microchip technology inc. figure 2-2: pic16f72 register file map indirect addr.(*) tmr0 pcl status fsr porta portb portc pclath intcon pir1 tmr1l tmr1h t1con tmr2 t2con sspbuf sspcon ccpr1l ccpr1h ccp1con option pcl status fsr trisatrisb trisc pclath intcon pie1 pcon pr2 sspstat 00h01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 file address indirect addr.(*) indirect addr.(*) pcl status fsr pclath intcon pcl status fsr pclath intcon 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh 17fh 1ffh bank 2 bank 3 indirect addr.(*) tmr0 option adres adcon0 adcon1 general purpose register accesses 20h-7fh trisb portb 96 bytes 10ch 10dh 10eh 10fh 110h 18ch 18dh 18eh 18fh 190h pmdatl pmadrl pmcon1 pmdath pmadrh unimplemented data memory locations, read as 0. * not a physical register. file address file address file address sspadd 120h 11fh 1a0h 19fh general purpose register 32 bytes bfh c0h accesses 40h-7fh accesses a0h -bfh 1bfh 1c0h accesses 40h -7fh downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 9 pic16f72 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is given in table 2-1. the special function registers can be classified into two sets: core (cpu) and peripheral. those registers associated with the core functions are described in detail in this section. those related to the operation of the peripheral features are described in detail in the peripheral feature section. table 2-1: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: bank 0 00h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 19 01h tmr0 timer0 modules register xxxx xxxx 27,13 02h (1) pcl program counter's (pc) least significant byte 0000 0000 18 03h (1) status irp rp1 rp0 to pd z dc c 0001 1xxx 12 04h (1) fsr indirect data memory address pointer xxxx xxxx 19 05h porta porta data latch when written: porta pins when read --0x 0000 21 06h portb portb data latch when written: portb pins when read xxxx xxxx 23 07h portc portc data latch when written: portc pins when read xxxx xxxx 25 08h unimplemented 09h unimplemented 0ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 18 0bh (1) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 14 0ch pir1 a d i f sspif ccp1if tmr2if tmr1if -0-- 0000 16 0dh unimplemented 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx 29 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx 29 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 29 11h tmr2 timer2 modules register 0000 0000 33 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 34 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx 43,48 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 45 15h ccpr1l capture/compare/pwm register (lsb) xxxx xxxx 38,39,41 16h ccpr1h capture/compare/pwm register (msb) xxxx xxxx 38,39,41 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 37 18h-1dh unimplemented 1eh adres a/d result register xxxx xxxx 53 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done a d o n 0000 00-0 53 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0, r = reserved. shaded locations are unimplemented, read as 0. note 1: these registers can be addressed from any bank. 2: the upper byte of the program counter is not directly access ible. pclath is a holding register for the pc<12:8> whose contents are transferred to the upper byte of the program counter. 3: this bit always reads as a 1. downloaded from: http:///
pic16f72 ds39597c-page 10 ? 2007 microchip technology inc. bank 1 80h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 19 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 13 82h (1) pcl program counter's (pc) least significant byte 0000 0000 18 83h (1) status irp rp1 rp0 to pd zd cc 0001 1xxx 12 84h (1) fsr indirect data memory address pointer xxxx xxxx 19 85h trisa porta data direction register --11 1111 21 86h trisb portb data direction register 1111 1111 23 87h trisc portc data direction register 1111 1111 25 88h unimplemented 89h unimplemented 8ah (1,2) pclath write buffer for the upper 5 bits of the pc ---0 0000 18 8bh (1) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 14 8ch pie1 a d i e sspie ccp1ie tmr2ie tmr1ie -0-- 0000 15 8dh unimplemented 8eh pcon p o r bor ---- --qq 17 8fh unimplemented 90h unimplemented 91h unimplemented 92h pr2 timer2 period register 1111 1111 41 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 43,48 94h sspstat smp cke d/a psr / w ua bf 0000 0000 44 95h unimplemented 96h unimplemented 97h unimplemented 98h unimplemented 99h unimplemented 9ah unimplemented 9bh unimplemented 9ch unimplemented 9dh unimplemented 9eh unimplemented 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 54 table 2-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0, r = reserved. shaded locations are unimplemented, read as 0. note 1: these registers can be addressed from any bank. 2: the upper byte of the program counter is not directly access ible. pclath is a holding register for the pc<12:8> whose contents are transferred to the upper byte of the program counter. 3: this bit always reads as a 1. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 11 pic16f72 bank 2 100h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 19 101h tmr0 timer0 modules register xxxx xxxx 27 102h (1 pcl program counter's (pc) least significant byte 0000 0000 18 103h (1) status irp rp1 rp0 to pd zd cc 0001 1xxx 12 104h (1) fsr indirect data memory address pointer xxxx xxxx 19 105h unimplemented 106h portb portb data latch when written: portb pins when read xxxx xxxx 23 107h unimplemented 108h unimplemented 109h unimplemented 10ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 18 10bh (1) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 14 10ch pmdatl data register low byte xxxx xxxx 35 10dh pmadrl address register low byte xxxx xxxx 35 10eh pmdath data register high byte --xx xxxx 35 10fh pmadrh address register high byte ---x xxxx 35 bank 3 180h (1) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 19 181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 13 182h (1) pcl program counter's (pc) least significant byte 0000 0000 18 183h (1) status irp rp1 rp0 to pd zd cc 0001 1xxx 12 184h (1) fsr indirect data memory address pointer xxxx xxxx 19 185h unimplemented 186h trisb portb data direction register 1111 1111 23 187h unimplemented 188h unimplemented 189h unimplemented 18ah (1,2) pclath write buffer for the upper 5 bits of the program counter ---0 0000 18 18bh (1) intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 14 18ch pmcon1 (3) r d 1--- ---0 35 18dh unimplemented 18eh reserved, maintain clear 0000 0000 18fh reserved, maintain clear 0000 0000 table 2-1: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0, r = reserved. shaded locations are unimplemented, read as 0. note 1: these registers can be addressed from any bank. 2: the upper byte of the program counter is not directly access ible. pclath is a holding register for the pc<12:8> whose contents are transferred to the upper byte of the program counter. 3: this bit always reads as a 1. downloaded from: http:///
pic16f72 ds39597c-page 12 ? 2007 microchip technology inc. 2.2.2.1 status register the status register, shown in register 2-1, contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect the z, c or dc bits from the status register. for other instructions, not affecting any status bits, see section 12.0, instruction set summary. register 2-1: status register (address 03h, 83h, 103h, 183h) note 1: the c and dc bits operate as a borrow and digit borrow bit, respectively, in sub- traction. see the sublw and subwf instructions for examples. r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zd c c bit 7 bit 0 bit 7 irp: register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) bit 6-5 rp<1:0>: register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes bit 4 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit ( addwf , addlw , sublw and subwf instructions) (1) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0 c: carry/borrow bit ( addwf , addlw , sublw and subwf instructions) (1,2) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow, the polarity is reversed. a subtraction is executed by adding the twos complement of the second operand. 2: for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 13 pic16f72 2.2.2.2 option register the option register is a readable and writable regis- ter that contains various control bits to configure the tmr0 prescaler/wdt postscaler (single assignable register known also as the prescaler), the external int interrupt, tmr0, and the weak pull-ups on portb. register 2-2: option register (address 81h, 181h) note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5 t0cs: tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clko) bit 4 t0se: tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps2:ps0: prescaler rate select bits legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown 000001 010 011 100 101 110 111 1 : 21 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate downloaded from: http:///
pic16f72 ds39597c-page 14 ? 2007 microchip technology inc. 2.2.2.3 intcon register the intcon register is a readable and writable regis- ter that contains various enable and flag bits for the tmr0 register overflow, rb port change and external rb0/int pin interrupts. register 2-3: intcon: interrupt control register (address 0bh, 8bh, 10bh, 18bh) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie tmr0ie inte rbie tmr0if intf rbif bit 7 bit 0 bit 7 gie: global interrupt enable bit 1 = enables all unmasked interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4 inte: rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 intf: rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 15 pic16f72 2.2.2.4 pie1 register this register contains the individual enable bits for the peripheral interrupts. register 2-4: pie1: peripheral interrupt enable register 1 (address 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 adie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 bit 7 unimplemented: read as 0 bit 6 adie: a/d converter interrupt enable bit 1 = enables the a/d converter interrupt 0 = disables the a/d converter interrupt bit 5-4 unimplemented: read as 0 bit 3 sspie: synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2 ccp1ie: ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie: tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
pic16f72 ds39597c-page 16 ? 2007 microchip technology inc. 2.2.2.5 pir1 register this register contains the individual flag bits for the peripheral interrupts. register 2-5: pir1: peripheral interrupt flag register 1 (address 0ch) u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 a d i f sspif ccp1if tmr2if tmr1if bit 7 bit 0 bit 7 unimplemented: read as 0 bit 6 adif: a/d converter interrupt flag bit 1 = an a/d conversion completed 0 = the a/d conversion is not complete bit 5-4 unimplemented: read as 0 bit 3 sspif: synchronous serial port (ssp) interrupt flag bit 1 = the ssp interrupt condition has occurred, and must be cleared in software before returning from the interrupt service routine. the conditions that will set this bit are a transmission/reception has taken place. 0 = no ssp interrupt condition has occurred bit 2 ccp1if: ccp1 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode bit 1 tmr2if: tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 17 pic16f72 2.2.2.6 pcon register the power control (pcon) register contains a flag bit to allow differentiation between a power-on reset (por), a brown-out reset, an external mclr reset and wdt reset. register 2-6: pcon: power control register (address 8eh) note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. note: bor is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bor is clear, indicating a brown-out has occurred. the bor status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the boren bit in the configuration word). u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-x p o r bor bit 7 bit 0 bit 7-2 unimplemented: read as 0 bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
pic16f72 ds39597c-page 18 ? 2007 microchip technology inc. 2.3 pcl and pclath the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 13-bits wide. the low byte is called the pcl register. this reg- ister is readable and writable. the high byte is called the pch register. this register contains the pc<12:8> bits and is not directly readable or writable. all updates to the pch register go through the pclath register. figure 2-3 shows the four situations for the loading of the pc. ? example 1 shows how the pc is loaded on a write to pcl (pclath<4:0> pch). ? example 2 shows how the pc is loaded during a goto instruction (pclath<4:3> pch). ? example 3 shows how the pc is loaded during a call instruction (pclath<4:3> pch), with the pc loaded (pushd) onto the top-of-stack. ? example 4 shows how the pc is loaded during one of the return instructions, where the pc is loaded (popd) from the top-of-stack. figure 2-3: loading of pc in different situations pc 12 8 7 0 5 pclath<4:0> pclath alu result opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl example 1 - instruction with pcl as destination example 2 - goto instruction stack (13-bits x 8) top-of-stack stack (13-bits x 8) to p - o f - sta c k opcode <10:0> pc 12 11 10 0 11 pclath<4:3> 87 2 pclath pch pcl example 3 - call instruction stack (13-bits x 8) top-of-stack opcode <10:0> pc 12 11 10 0 11 87 pclath pch pcl example 4 - return , retfie , or retlw instruction stack (13-bits x 8) top-of-stack 13 13 note: pclath is not updated with the contents of pch. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 19 pic16f72 2.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). refer to the application note, implementing a table read" (an556). 2.3.2 stack the stack allows a combination of up to eight program calls and interrupts to occur. the stack contains the return address from this branch in program execution. mid-range devices have an 8-level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushd onto the stack when a call instruction is executed, or an interrupt causes a branch. the stack is popd in the event of a return, retlw or a retfie instruction execution. pclath is not modified when the stack is pushd or popd. after the stack has been pushd eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). an example of the overwriting of the stack is shown in figure 2-4. figure 2-4: stack modification 2.4 program memory paging the call and goto instructions provide 11 bits of address to allow branching within any 2k program memory page. when doing a call or goto instruction, the upper two bits of the address are provided by pclath<4:3>. when doing a call or goto instruc- tion, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. if a return from a call instruction (or interrupt) is executed, the entire 13-bit pc is pushed onto the stack. therefore, manipulation of the pclath<4:3> bits is not required for the return instructions (which pops the address from the stack). 2.5 indirect addressing, indf and fsr registers the indf register is not a physical register. address- ing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 2-1. example 2-1: indirect addressing an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 2-5. note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw and retfie instructions, or the vectoring to an interrupt address. push1 push9 push2 push10 push3 push4 push5 push6 push7 push8 top-of-stack stack note: the pic16f72 device ignores the paging bit pclath<4:3>. the use of pclath<4:3> as a general purpose read/ write bit is not recommended, since this may affect upward compatibility with future products. movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue downloaded from: http:///
pic16f72 ds39597c-page 20 ? 2007 microchip technology inc. figure 2-5: direct/indirect addressing note 1: for register file map detail, see figure 2-2. data memory (1) indirect addressing direct addressing bank select location select rp1:rp0 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 ffh 80h 7fh 00h 17fh 100h 1ffh 180h downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 21 pic16f72 3.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. additional information on i/o ports may be found in the pic? mid-range mcu reference manual, (ds33023). 3.1 porta and the trisa register porta is a 6-bit wide, bi-directional port. the corre- sponding data direction register is trisa. setting a trisa bit (= 1) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisa bit (= 0) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). reading the porta register, reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. pin ra4 is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/t0cki pin is a schmitt trigger input and an open drain output. all other ra port pins have ttl input levels and full cmos output drivers. other porta pins are multiplexed with analog inputs and analog v ref input. the operation of each pin is selected by clearing/setting the control bits in the adcon1 register (a/d control register1). the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 3-1: initializing porta figure 3-1: block diagram of ra3:ra0 and ra5 pins figure 3-2: block diagram of ra4/t0cki pin note: on a power-on reset, these pins are con- figured as analog inputs and read as 0. banksel porta ; select bank for porta clrf porta ; initialize porta by ; clearing output ; data latches banksel adcon1 ; select bank for adcon1 movlw 0x06 ; configure all pins movwf adcon1 ; as digital inputs movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs ; trisa<7:6> are always ; read as ?0?. data bus q d q ck q d q ck qd en p n wr port wr tris data latch tris latch rd tris rd port v ss v dd i/o pin analog input mode ttl input buffer to a/d converter v dd v ss data bus wrport wrtris rd port data latch tris latch rd tris schmitt trigger input buffer n v ss i/o pin tmr0 clock input q d q ck q d q ck en qd en v ss downloaded from: http:///
pic16f72 ds39597c-page 22 ? 2007 microchip technology inc. table 3-1: porta functions table 3-2: summary of registers associated with porta name bit# buffer function ra0/an0 bit 0 ttl input/output or analog input. ra1/an1 bit 1 ttl input/output or analog input. ra2/an2 bit 2 ttl input/output or analog input. ra3/an3/v ref bit 3 ttl input/output or analog input or v ref . ra4/t0cki bit 4 st input/output or external clock input for timer0. output is open drain type. ra5/an4/ss bit 5 ttl input/output or analog input or slave select input for synchronous serial port. legend: ttl = ttl input, st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 05h porta ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa porta data direction register --11 1111 --11 1111 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 legend: x = unknown, u = unchanged, - = unimplemented locations read as 0. shaded cells are not used by porta. note: when using the ssp module in spi slave mode and ss enabled, the a/d port configuration control bits (pcfg2:pcfg0) in the a/d control register (adcon1) must be set to one of the following configurations: 100, 101, 11x . downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 23 pic16f72 3.2 portb and the trisb register portb is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisb. setting a trisb bit (= 1) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisb bit (= 0) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). example 3-2: initializing portb each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (option<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. figure 3-3: block diagram of rb3:rb0 pins four of portbs pins, rb7:rb4, have an interrupt-on- change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt on change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the mismatch outputs of rb7:rb4 are ord together to generate the rb port change interrupt with flag bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. this interrupt-on-mismatch feature, together with soft- ware configurable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. refer to the embedded control handbook, implementing wake-up on key stroke (an552). rb0/int is an external interrupt input pin and is configured using the intedg bit (option<6>). figure 3-4: block diagram of rb7:rb4 pins banksel portb ; select bank for portb clrf portb ; initialize portb by ; clearing output ; data latches banksel trisb ; select bank for trisb movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs data latch rbpu (1) p v dd q d ck q d ck qd en data wr wr rd tris rd port weak pull-up rd port rb0/int i/o pin ttl input buffer note 1: to enable weak pull-ups, set the appropriate tris bit(s) schmitt trigger buffer tris latch v dd v ss and clear the rbpu bit (option<7>). bus port tris data latch from other rbpu (1) p v dd i/o pin q d ck q d ck qd en qd en data wr wr set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl input buffer note 1: to enable weak pull-ups, set the appropriate tris bit(s) st buffer rb7:rb6 in serial programming mode q3 q1 v dd v ss and clear the rbpu bit (option<7>). bus port tris downloaded from: http:///
pic16f72 ds39597c-page 24 ? 2007 microchip technology inc. table 3-3: portb functions table 3-4: summary of registers associated with portb name bit# buffer function rb0/int bit 0 ttl/st (1) input/output pin or external interrupt input. internal software programmable weak pull-up. rb1 bit 1 ttl input/output pin. internal software programmable weak pull-up. rb2 bit 2 ttl input/output pin. internal software programmable weak pull-up. rb3 bit 3 ttl input/output pin. internal software programmable weak pull-up. rb4 bit 4 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb5 bit 5 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb6 bit 6 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming clock. rb7 bit 7 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 06h, 106h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h, 186h trisb portb data direction register 1111 1111 1111 1111 81h, 181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged. shaded cells are not used by portb. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 25 pic16f72 3.3 portc and the trisc register portc is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisc. setting a trisc bit (= 1) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisc bit (= 0) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). portc is multiplexed with several peripheral functions (table 3-5). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. since the tris bit override is in effect while the peripheral is enabled, read-modify- write instructions ( bsf, bcf, xorwf ) with trisc as destination should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings. example 3-3: initializing portc figure 3-5: portc block diagram (peripheral output override) banksel portc ; select bank for portc clrf portc ; initialize portc by ; clearing output ; data latches banksel trisc ; select bank for trisc movlw 0xcf ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs port/peripheral select (1) data wr port wr tris rd data latch tris latch rd tris schmitt trigger q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss port peripheral oe (2) peripheral input note 1: port/peripheral select signal selects between port data and peripheral output. 2: peripheral oe (output enable) is only activated if peripheral select is active. v ss i/o pin v dd bus downloaded from: http:///
pic16f72 ds39597c-page 26 ? 2007 microchip technology inc. table 3-5: portc functions table 3-6: summary of registers associated with portc name bit# buffer type function rc0/t1oso/t1cki bit 0 st input/output port pin or timer1 oscillator output/timer1 clock input. rc1/t1osi bit 1 st input/output port pin or timer1 oscillator input. rc2/ccp1 bit 2 st input/output port pin or capture1 input/compare1 output/pwm1 output. rc3/sck/scl bit 3 st rc3 can also be the synchronous serial clock for both spi and i 2 c modes. rc4/sdi/sda bit 4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit 5 st input/output port pin or synchronous serial port data output. rc6 bit 6 st input/output port pin. rc7 bit 7 st input/output port pin. legend: st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 27 pic16f72 4.0 timer0 module the timer0 module timer/counter has the following features: ? 8-bit timer/counter ? readable and writable ? 8-bit software programmable prescaler ? internal or external clock select ? interrupt on overflow from ffh to 00h ? edge select for external clock figure 4-1 is a block diagram of the timer0 module and the prescaler shared with the wdt. additional information on the timer0 module is available in the pic? mid-range mcu family reference manual (ds33023). 4.1 timer0 operation timer mode is selected by clearing bit t0cs (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option<5>). in counter mode, timer0 will incre- ment, either on every rising or falling edge of pin ra4/ t0cki. the incrementing edge is determined by the timer0 source edge select bit t0se (option<4>). clearing bit t0se selects the rising edge. restrictions on the external clock input are discussed in detail in section 4.3. the prescaler is mutually exclusively shared between the timer0 module and the watchdog timer. the pres- caler is not readable or writable. section 4.4 details the operation of the prescaler. 4.2 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h. this overflow sets bit tmr0if (intcon<2>). the interrupt can be masked by clearing bit tmr0ie (intcon<5>). bit tmr0if must be cleared in software by the timer0 module interrupt service routine, before re-enabling this inter- rupt. the tmr0 interrupt cannot awaken the processor from sleep, since the timer is shut-off during sleep. figure 4-1: block diagram of the timer0/wdt prescaler ra4/t0cki t0se pin m u x clko (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 01 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are (option<5:0>). psa wdt enable bit m u x 01 0 1 data bus set flag bit tmr0if on overflow 8 psa t0cs prescaler downloaded from: http:///
pic16f72 ds39597c-page 28 ? 2007 microchip technology inc. 4.3 using timer0 with an external clock when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki, with the internal phase clocks, is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, it is necessary for t0cki to be high for at least 2 t osc (and a small rc delay of 20 ns) and low for at least 2 t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. 4.4 prescaler there is only one prescaler available, which is mutually exclusively shared between the timer0 module and the watchdog timer. a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer, and vice-versa. this prescaler is not readable or writable (see figure 4-1). the psa and ps2:ps0 bits (option<3:0>) determine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. the prescaler is not readable or writable. table 4-1: registers associated with timer0 note: writing to tmr0 when the prescaler is assigned to timer0, will clear the prescaler count but will not change the prescaler assignment. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 01h,101h tmr0 timer0 module register xxxx xxxx uuuu uuuu 0bh,8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 81h,181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as 0. shaded cells are not used by timer0. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 29 pic16f72 5.0 timer1 module the timer1 module timer/counter has the following features: ? 16-bit timer/counter (two 8-bit registers; tmr1h and tmr1l) ? readable and writable (both registers) ? internal or external clock select ? interrupt on overflow from ffffh to 0000h ? reset from ccp module trigger timer1 has a control register, shown in register 5-1. timer1 can be enabled/disabled by setting/clearing control bit tmr1on (t1con<0>). figure 5-2 is a simplified block diagram of the timer1 module. additional information on timer modules is available in the pic? mid-range mcu reference manual, (ds33023). 5.1 timer1 operation timer1 can operate in one of these modes: ?as a timer ? as a synchronous counter ? as an asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored. timer1 also has an internal reset input. this reset can be generated by the ccp module (section 8.0). register 5-1: t1con: timer1 control regist er (address 10h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7-6 unimplemented: read as 0 bit 5-4 t1ckps1:t1ckps0: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable control bit 1 = oscillator is enabled 0 = oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain.) bit 2 t1sync : timer1 external clock input synchronization control bit tmr1cs = 1: 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0: this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t1cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
pic16f72 ds39597c-page 30 ? 2007 microchip technology inc. 5.2 timer1 operation in timer mode timer mode is selected by clearing the tmr1cs (t1con<1>) bit. in this mode, the input clock to the timer is f osc /4. the synchronize control bit t1sync (t1con<2>) has no effect, since the internal clock is always in sync. 5.3 timer1 counter operation timer1 may operate in asynchronous or synchronous mode, depending on the setting of the tmr1cs bit. when timer1 is being incremented via an external source, increments occur on a rising edge. after timer1 is enabled in counter mode, the module must first have a falling edge before the counter begins to increment. 5.4 timer1 operation in synchronized counter mode counter mode is selected by setting bit tmr1cs. in this mode, the timer increments on every rising edge of clock input on pin rc1/t1osi when bit t1oscen is set, or on pin rc0/t1oso/t1cki when bit t1oscen is cleared. if t1sync is cleared, then the external clock input is synchronized with internal phase clocks. the synchro- nization is done after the prescaler stage. the prescaler stage is an asynchronous ripple counter. in this configuration, during sleep mode, timer1 will not increment even if the external clock is present, since the synchronization circuit is shut-off. the prescaler, however, will continue to increment. figure 5-1: timer1 incrementing edge figure 5-2: timer1 block diagram t1cki (default high) t1cki (default low) note: arrows indicate counter increments. tmr1h tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 q clock t1oscen enable oscillator (1) f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 10 01 synchronized clock input 2 rc0/t1oso/t1cki rc1/t1osi note 1: when the t1oscen bit is cleared, the inverter is turned off. this eliminates power drain. set flag bit tmr1if on overflow tmr1 (2) downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 31 pic16f72 5.5 timer1 operation in asynchronous counter mode if control bit t1sync (t1con<2>) is set, the external clock input is not synchronized. the timer continues to increment asynchronous to the internal phase clocks. the timer will continue to run during sleep and can generate an interrupt on overflow, that will wake-up the processor. however, special precautions in software are needed to read/write the timer (section 5.5.1). in asynchronous counter mode, timer1 cannot be used as a time base for capture or compare operations. 5.5.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write conten- tion may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the timer register. data in the timer1 register (tmr1) may become corrupted. cor- ruption occurs when the timer enable is turned off at the same instant that a ripple carry occurs in the timer module. reading the 16-bit value requires some care. exam- ples 12-2 and 12-3 in the pic? mid-range mcu family reference manual (ds33023) show how to read and write timer1 when it is running in asynchronous mode. 5.6 timer1 oscillator a crystal oscillator circuit is built between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con<3>). the oscilla- tor is a low power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for a 32 khz crystal. table 5-1 shows the capacitor selection for the timer1 oscillator. the timer1 oscillator is identical to the lp oscillator. the user must provide a software time delay to ensure proper oscillator start-up. table 5-1: capacitor selection for the timer1 oscillator 5.7 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/ clearing tmr1 interrupt enable bit tmr1ie (pie1<0>). 5.8 resetting timer1 using a ccp trigger output if the ccp module is configured in compare mode to generate a special event trigger" signal (ccp1m3:ccp1m0 = 1011) , the signal will reset timer1 and start an a/d conversion (if the a/d module is enabled). timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a special event trigger from ccp1, the write will take precedence. in this mode of operation, the ccpr1h:ccpr1l regis- ters pair effectively becomes the period register for timer1. osc type freq c1 c2 lp 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf these values are for design guidance only. note 1: higher capacitance increases the stability of oscillator, but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. note: the special event triggers from the ccp1 module will not set interrupt flag bit tmr1if (pir1<0>). downloaded from: http:///
pic16f72 ds39597c-page 32 ? 2007 microchip technology inc. 5.9 resetting timer1 register pair (tmr1h, tmr1l) tmr1h and tmr1l registers are not reset to 00h on a por, or any other reset, except by the ccp1 special event triggers. t1con register is reset to 00h on a power-on reset or a brown-out reset, which shuts off the timer and leaves a 1:1 prescale. in all other resets, the register is unaffected. 5.10 timer1 prescaler the prescaler counter is cleared on writes to the tmr1h or tmr1l registers. table 5-2: registers associated with timer1 as a timer/counter address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as 0. shaded ce lls are not used by the timer1 module. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 33 pic16f72 6.0 timer2 module the timer2 module timer has the following features: ? 8-bit timer (tmr2 register) ? 8-bit period register (pr2) ? readable and writable (both registers) ? software programmable prescaler (1:1, 1:4, 1:16) ? software programmable postscaler (1:1 to 1:16) ? interrupt on tmr2 match of pr2 ? ssp module optional use of tmr2 output to generate clock shift timer2 has a control register, shown in register 6-1. timer2 can be shut-off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. figure 6-1 is a simplified block diagram of the timer2 module. additional information on timer modules is available in the pic? mid-range mcu reference manual, (ds33023). 6.1 timer2 operation timer2 can be used as the pwm time-base for pwm mode of the ccp module. the tmr2 register is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con<1:0>). the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if, (pir1<1>)). 6.2 timer2 prescaler and postscaler the prescaler and postscaler counters are cleared when any of the following occurs: ? a write to the tmr2 register ? a write to the t2con register ? any device reset (power-on reset, mclr , wdt reset, or brown-out reset) tmr2 is not cleared when t2con is written. 6.3 timer2 interrupt the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. 6.4 output of tmr2 the output of tmr2 (before the postscaler) is fed to the synchronous serial port module, which optionally uses it to generate a shift clock. figure 6-1: timer2 block diagram comparator tmr2 sets flag tmr2 reg output (1) reset postscaler prescaler pr2 reg 2 f osc /4 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. to downloaded from: http:///
pic16f72 ds39597c-page 34 ? 2007 microchip technology inc. register 6-1: t2con: timer2 control regist er (address 12h) table 6-1: registers associated with timer2 as a timer/counter u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as 0 bit 6-3 toutps3:toutps0: timer2 output postscale select bits 0000 =1:1 postscale 0001 =1:2 postscale 0010 =1:3 postscale ?? ? 1111 = 1:16 postscale bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0: timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh, 10bh, 18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 0000 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 0000 0000 11h tmr2 timer2 module register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as 0. shaded ce lls are not used by the timer2 module. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 35 pic16f72 7.0 reading pr ogram memory the flash program memory is readable during nor- mal operation over the entire v dd range. it is indirectly addressed through special function registers (sfr). up to 14-bit wide numbers can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ascii, etc. executing a program memory location containing data that forms an invalid instruction results in a nop . there are five sfrs used to read the program and memory: ?pmcon1 ?pmdatl ?pmdath ? pmadrl ? pmadrh the program memory allows word reads. program memory access allows for checksum calculation and reading calibration tables. when interfacing to the program memory block, the pmdath:pmdatl registers form a two-byte word, which holds the 14-bit data for reads. the pmadrh:pmadrl registers form a two-byte word, which holds the 13-bit address of the flash location being accessed. this device has up to 2k words of program flash, with an address range from 0h to 07ffh. the unused upper bits pmdath<7:6> and pmadrh<7:5> are not implemented and read as zeros. 7.1 pmadr the address registers can address up to a maximum of 8k words of program flash. when selecting a program address value, the msbyte of the address is written to the pmadrh register and the lsbyte is written to the pmadrl register. the upper msbits of pmadrh must always be clear. 7.2 pmcon1 register pmcon1 is the control register for memory accesses. the control bit rd initiates read operations. this bit cannot be cleared, only set, in software. it is cleared in hardware at the completion of the read operation. register 7-1: pmcon1: program memory control regist er 1 (address 18ch) r-1 u-0 u-0 u-0 u-0 u-0 u-0 r/s-0 reserved r d bit 7 bit 0 bit 7 reserved: read as 1 bit 6-1 unimplemented: read as 0 bit 0 rd: read control bit 1 = initiates a flash read, rd is cleared in hardware. the rd bit can only be set (not cleared) in software. 0 = does not initiate a flash read legend: w = writable bit u = unimplemented bit, read as 0 r = readable bit s = settable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
pic16f72 ds39597c-page 36 ? 2007 microchip technology inc. 7.3 reading the flash program memory to read a program memory location, the user must write two bytes of the address to the pmadrl and pmadrh registers and then set control bit, rd (pmcon1<0>). once the read control bit is set, the program memory flash controller will use the second instruction cycle after to read the data. this causes the second instruction immediately following the bsf pmcon1,rd instruction to be ignored. the data is available in the very next cycle in the pmdatl and pmdath registers; therefore, it can be read as two bytes in the following instructions. pmdatl and pmdath registers will hold this value until another read, or until it is written to by the user (during a write operation). 7.4 operation during code protect the flash program memory control can read any- where within the program memory, whether or not the program memory is code protected. this does not compromise the code, because there is no way to rewrite a portion of the program memory, or leave contents of a program memory read in a register while changing modes. example 7-1: flash program read table 7-1: registers associated with program flash banksel pmadrh ; select bank for pmadrh movlw ms_prog_ee_addr ; movwf pmadrh ; ms byte of program address to read movlw ls_prog_ee_addr ; movwf pmadrl ; ls byte of program address to read banksel pmcon1 ; select bank for pmcon1 bsf pmcon1, rd ; ee read ; nop ; any instructions here are ignored as program nop ; memory is read in second cycle after bsf pmcon1,rd ; ; first instruction after bsf pmcon1,rd executes normally banksel pmdatl ; select bank for pmdatl movf pmdatl, w ; w = ls byte of program pmdatl movf pmdath, w ; w = ms byte of program pmdatl address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 10dh pmadrl address register low byte xxxx xxxx uuuu uuuu 10fh pmadrh address register high byte xxxx xxxx uuuu uuuu 10ch pmdatl data register low byte xxxx xxxx uuuu uuuu 10eh pmdath data register high byte xxxx xxxx uuuu uuuu 18ch pmcon1 (1) rd 1--- ---0 1--- ---0 legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'. shaded cells are not used during flash access. note 1: this bit always reads as a 1. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 37 pic16f72 8.0 capture/compare/pwm (ccp) module the ccp (capture/compare/pwm) module contains a 16-bit register that can operate as a: ? 16-bit capture register ? 16-bit compare register ? pwm master/slave duty cycle register. table 8-1 shows the timer resources of the ccp module modes. capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. all are readable and writable. additional information on the ccp module is available in the pic? mid-range mcu reference manual, (ds33023). table 8-1: ccp mode - timer resource register 8-1: ccpcon1: capture/compare/pwm control register 1 (address 17h) ccp mode timer resource capture compare pwm timer1 timer1 timer2 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ccpxx ccpxy ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5-4 ccpxx:ccpxy: pwm least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprxl. bit 3-0 ccpxm3:ccpxm0: ccpx mode select bits 0000 = capture/compare/pwm disabled (resets ccpx module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccpxif bit is set) 1001 = compare mode, clear output on match (ccpxif bit is set) 1010 = compare mode, generate software interrupt on match (ccpxif bit is set, ccpx pin is unaffected) 1011 = compare mode, trigger special event (ccpxif bit is set, ccpx pin is unaffected); ccp1 resets tmr1 and starts an a/d conversion (if a/d module is enabled) 11xx = pwm mode legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
pic16f72 ds39597c-page 38 ? 2007 microchip technology inc. 8.1 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on pin rc2/ccp1. an event is defined as: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge an event is selected by control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit ccp1if (pir1<2>) is set. it must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value is overwritten by the new captured value. 8.1.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be configured as an input by setting the trisc<2> bit. figure 8-1: capture mode operation block diagram 8.1.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. 8.1.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<2>) clear to avoid false interrupts and should clear the flag bit ccp1if, following any such change in operating mode. 8.1.4 ccp prescaler there are four prescaler settings, specified by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. example 8-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the false interrupt. example 8-1: changing between capture prescalers note: if the rc2/ccp1 is configured as an out- put, a write to the port can cause a capture condition. ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<2>) capture enable qs ccp1con<3:0> rc2/ccp1 prescaler 1, 4, 16 and edge detect pin clrf ccp1con ; turn ccp module off movlw new_capt_ps ; load the w reg with ; the new prescaler ; mode value and ccp on movwf ccp1con ; load ccp1con with ; this value downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 39 pic16f72 8.2 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rc2/ccp1 pin is: ? driven high ?driven low ? remains unchanged the action on the pin is based on the value of control bits ccp1m3:ccp1m0 (ccp1con<3:0>). at the same time, interrupt flag bit ccp1if is set. the output may become inverted when the mode of the module is changed from compare/clear on match (ccpxm<3:0> = 1001 ) to compare/set on match (ccpxm<3:0> = 1000 ). this may occur as a result of any operation that selectively clears bit ccpxm0, such as a bcf instruction. when this condition occurs, the output becomes inverted when the instruction is executed. it will remain inverted for all following compare operations, until the module is reset. figure 8-2: compare mode operation block diagram 8.2.1 ccp pin configuration the user must configure the rc2/ccp1 pin as an output by clearing the trisc<2> bit. 8.2.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode, if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 8.2.3 software interrupt mode when generate software interrupt is chosen, the ccp1 pin is not affected. only a ccp interrupt is generated (if enabled). 8.2.4 special event trigger in this mode, an internal hardware trigger is generated that may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special trigger output of ccp1 resets the tmr1 register pair, and starts an a/d conversion (if the a/d module is enabled). ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if (pir1<2>) match rc2/ccp1 trisc<2> ccp1con<3:0> mode select output enable pin special event trigger will: ? reset timer1, but not set interrupt flag bit tmr1if (pir1<0>) ? set bit go/done (adcon0<2>) bit, which starts an a/d conversion note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the data latch. note: the special event trigger from the ccp1 module will not set interrupt flag bit tmr1if (pir1<0>). downloaded from: http:///
pic16f72 ds39597c-page 40 ? 2007 microchip technology inc. table 8-2: registers associated with capture, compare, and timer1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 0000 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as 0. shaded ce lls are not used by capture and timer1. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 41 pic16f72 8.3 pwm mode in pulse width modulation (pwm) mode, the ccp1 pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 8-3 shows a simplified block diagram of the ccp module in pwm mode. for a step by step procedure on how to set up the ccp module for pwm operation, see section 8.3.3. figure 8-3: simplified pwm block diagram a pwm output (figure 8-4) has a time-base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 8-4: pwm output 8.3.1 pwm period the pwm period is specified by writing to the pr2 reg- ister. the pwm period can be calculated using the formula in equation 8-1. equation 8-1: pwm period pwm frequency is defined as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ?tmr2 is cleared ? the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) ? the pwm duty cycle is latched from ccpr1l into ccpr1h 8.3.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available: the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. equation 8-2 is used to calculate the pwm duty cycle in time. equation 8-2: pwm duty cycle ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 ( note 1 ) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 note 1: 8-bit timer is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time-base. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 note: the timer2 postscaler (see section 6.0) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. pwmperiod= [(pr2)+1]?4?t osc ? (tmr2 prescale value) pwm duty cycle = (ccpr1l:ccp1con<5:4>) ? t osc ? (tmr2 prescale value) downloaded from: http:///
pic16f72 ds39597c-page 42 ? 2007 microchip technology inc. maximum pwm resolution (bits) for a given pwm frequency is calculated using equation 8-3. equation 8-3: pwm max resolution for a sample pwm period and duty cycle calculation, see the pic? mid-range mcu reference manual (ds33023). 8.3.3 set-up for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. table 8-3: example pwm frequencies and resolutions at 20 mhz table 8-4: registers associated with pwm and timer2 note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. log ( f pwm log(2) f osc ) bits pwm maximum resolution = pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescaler (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 5.5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 0000 0000 8ch pie1 adie sspie ccp1ie tmr2ie tmr1ie -0-- 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 11h tmr2 timer2 module register 0000 0000 0000 0000 92h pr2 timer2 module period register 1111 1111 1111 1111 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as 0. shaded cells are not used by pwm and timer2. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 43 pic16f72 9.0 synchronous serial port (ssp) module 9.1 ssp module overview the synchronous serial port (ssp) module is a serial interface useful for communicating with other periph- eral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the ssp module can operate in one of two modes: ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c) an overview of i 2 c operations and additional informa- tion on the ssp module can be found in the pic? mid-range mcu family reference manual (ds33023). refer to application note an578, use of the ssp module in the i 2 c multi-master environment. 9.2 spi mode this section contains register definitions and operational characteristics of the spi module. spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. to accomplish communication, typically three pins are used: ? serial data out (sdo) rc5/sdo ? serial data in (sdi) rc4/sdi/sda ? serial clock (sck) rc3/sck/scl additionally, a fourth pin may be used when in a slave mode of operation: ? slave select (ss ) ra5/an4/ss when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits in the sspcon register (sspcon<5:0>) and sspstat<7:6>. these control bits allow the following to be specified: ? master mode (sck is the clock output) ? slave mode (sck is the clock input) ? clock polarity (idle state of sck) ? clock edge (output data on rising/falling edge of sck) ? clock rate (master mode only) ? slave select mode (slave mode only) downloaded from: http:///
pic16f72 ds39597c-page 44 ? 2007 microchip technology inc. register 9-1: sspstat: synchronous serial port status register (address 94h) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr / w ua bf bit 7 bit 0 bit 7 smp: spi data input sample phase bits spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time (microwire ? ) spi slave mode: smp must be cleared when spi is used in slave mode i 2 c mode: this bit must be maintained clear bit 6 cke: spi clock edge select bits (figure 9-2, figure 9-3, and figure 9-4) spi mode, ckp = 0: 1 = data transmitted on rising edge of sck (microwire alternate) 0 = data transmitted on falling edge of sck spi mode, ckp = 1: 1 = data transmitted on falling edge of sck (microwire default) 0 = data transmitted on rising edge of sck i 2 c mode: this bit must be maintained clear bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was addre ss bit 4 p: stop bit (i 2 c mode only) C this bit is cleared when the ssp module is disabled, or when the start bit is detected last. sspen is cleared. 1 = indicates that a stop bit has been detected last (this bit is 0 on reset) 0 = stop bit was not detected last bit 3 s: start bit (i 2 c mode only) C this bit is cleared when the ssp module is disabled, or when the stop bit is detected last. sspen is cleared. 1 = indicates that a start bit has been detected last (this bit is 0 on reset) 0 = start bit was not detected last bit 2 r/w : read/write information bit (i 2 c mode only) C this bit holds the r/w bit information follow- ing the last address match. this bit is only valid from the address match to t he next start bit, stop bit, or ack bit. 1 =read 0 = write bit 1 ua: update address bit (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit receive (spi and i 2 c modes): 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit (i 2 c mode only): 1 = transmit in progress, sspbuf is full 0 = transmit complete, sspbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 45 pic16f72 register 9-2: sspcon: sync serial port control register (address 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit in spi mode : 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting overflow. in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. 0 = no overflow in i 2 c mode: 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a "dont care" in transmit mode. sspov must be cleared in software in either mode. 0 = no overflow bit 5 sspen: synchronous serial port enable bit in spi mode : 1 = enables serial port and configures sck, sdo, and sdi as serial port pins 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and configures the sda and scl pins as serial port pins 0 = disables serial port and configures these pins as i/o port pins in both modes, when enabled, these pins must be properly configured as input or output. bit 4 ckp: clock polarity select bit in spi mode : 1 = idle state for clock is a high level (microwire ? default) 0 = idle state for clock is a low level (microwire alternate) in i 2 c mode: sck release control 1 = enable clock 0 = holds clock low (clock stretch - used to ensure data setup time) bit 3-0 sspm<3:0>: synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin. 0110 =i 2 c slave mode, 7-bit address 0111 =i 2 c slave mode, 10-bit address 1011 =i 2 c firmware controlled master mode (slave idle) 1110 =i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 =i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
pic16f72 ds39597c-page 46 ? 2007 microchip technology inc. figure 9-1: ssp block diagram (spi mode) to enable the serial port, ssp enable bit, sspen (sspcon<5>) must be set. to reset or reconfigure spi mode, clear bit sspen, re-initialize the sspcon reg- ister, and then set bit sspen. this configures the sdi, sdo, sck, and ss pins as serial port pins. for the pins to behave as the serial port function, they must have their data direction bits (in the trisc register) appropriately programmed. that is: ? sdi must have trisc<4> set ? sdo must have trisc<5> cleared ? sck (master mode) must have trisc<3> cleared ? sck (slave mode) must have trisc<3> set ?ss must have trisa<5> set and adcon must be configured such that ra5 is a digital i/o . table 9-1: registers associated with spi operation read write internal data bus rc4/sdi/sda rc5/sdo ra5/an4/ss rc3/sck/ sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t cy prescaler 4, 16, 64 trisc<3> 2 edge select 2 4 scl note 1: when the spi is in slave mode with ss pin control enabled (sspcon<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke = 1, then the ss pin control must be enabled. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 adif sspif ccp1if tmr2if tmr1if -0-- 0000 0000 0000 8ch pie1 adie s s p i e ccp1ie tmr2ie tmr1ie -0-- 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 85h trisa porta data direction register --11 1111 --11 1111 94h sspstat d/a p s r/w ua bf --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as 0. shaded cells are not used by the ssp in spi mode. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 47 pic16f72 figure 9-2: spi mode timing, master mode figure 9-3: spi mode timing (slave mode with cke = 0) figure 9-4: spi mode timing (slave mode with cke = 1) sck (ckp = 0, sdi (smp = 0) sspif bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sdi (smp = 1) sck (ckp = 0, sck (ckp = 1, sck (ckp = 1, sdo bit7 bit7 bit0 bit0 cke = 0) cke = 1) cke = 0) cke = 1) sck (ckp = 0) sdi (smp = 0) sspif bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sck (ckp = 1) sdo bit7 bit0 ss (optional) sck (ckp = 0) sdi (smp = 0) sspif bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sck (ckp = 1) sdo bit7 bit0 ss downloaded from: http:///
pic16f72 ds39597c-page 48 ? 2007 microchip technology inc. 9.3 ssp i 2 c mode operation the ssp module in i 2 c mode fully implements all slave functions, except general call support and provides interrupts on start and stop bits in hardware to facilitate firmware implementations of the master func- tions. the ssp module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. two pins are used for data transfer. these are the rc3/ sck/scl pin, which is the clock (scl), and the rc4/ sdi/sda pin, which is the data (sda). the user must configure these pins as inputs or outputs through the trisc<4:3> bits. the ssp module functions are enabled by setting ssp enable bit sspen (sspcon<5>). figure 9-5: ssp block diagram (i 2 c mode) the ssp module has five registers for i 2 c operation: ? ssp control register (sspcon) ? ssp status register (sspstat) ? serial receive/transmit buffer (sspbuf) ? ssp shift register (sspsr) - not directly accessible ? ssp address register (sspadd) the sspcon register allows control of the i 2 c opera- tion. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: ?i 2 c slave mode (7-bit address) ?i 2 c slave mode (10-bit address) ?i 2 c slave mode (7-bit address), with start and stop bit interrupts enabled ?i 2 c slave mode (10-bit address), with start and stop bit interrupts enabled ?i 2 c firmware controlled master operation, slave is idle selection of any i 2 c mode, with the sspen bit set, forces the scl and sda pins to be open drain, pro- vided these pins are programmed to inputs by setting the appropriate trisc bits. additional information on ssp i 2 c operation may be found in the pic? mid-range mcu reference manual (ds33023). 9.3.1 slave mode in slave mode, the scl and sda pins must be config- ured as inputs (trisc<4:3> set). the ssp module will override the input state with the output data when required (slave-transmitter). when an address is matched or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse, and then load the sspbuf register with the received value currently in the sspsr register. either or both of the following conditions will cause the ssp module not to give this ack pulse. a) the buffer full bit bf (sspstat<0>) was set before the transfer was received. b) the overflow bit sspov (sspcon<6>) was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir1<3>) is set. table 9-2 shows what happens when a data transfer byte is received, given the status of bits bf and sspov. the shaded cells show the condition where user software did not properly clear the overflow condi- tion. flag bit bf is cleared by reading the sspbuf register while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the ssp module are shown in timing parameter #100 and parameter #101. 9.3.1.1 addressing once the ssp module has been enabled, it waits for a start condition to occur. following the start condi- tion, the eight bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register. b) the buffer full bit, bf is set. c) an ack pulse is generated. d) ssp interrupt flag bit, sspif (pir1<3>) is set (interrupt is generated, if enabled) - on the falling edge of the ninth scl pulse. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg ) rc3/sck/scl rc4/ shift clock msb sdi/ lsb sda downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 49 pic16f72 in 10-bit address mode, two address bytes need to be received by the slave device. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address the first byte would equal 1111 0 a9 a8 0 , where a9 and a8 are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7- 9 for slave-transmitter: 1. receive first (high) byte of address (bits sspif, bf, and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf, and ua are set). 5. update the sspadd register with the first (high) byte of address, if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif. 9.3.1.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte overflow condition exists, then a no acknowledge (ack ) pulse is given. an overflow condition is indicated if either bit bf (sspstat<0>) is set, or bit sspov (sspcon<6>) is set. an ssp interrupt is generated for each data transfer byte. flag bit sspif (pir1<3>) must be cleared in soft- ware. the sspstat register is used to determine the status of the byte. 9.3.1.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit, and pin rc3/sck/scl is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr regis- ter. then pin rc3/sck/scl should be enabled by set- ting bit ckp (sspcon<4>). the master device must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master device by stretching the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 9-7). an ssp interrupt is generated for each data transfer byte. flag bit sspif must be cleared in software and the sspstat register is used to determine the status of the byte. flag bit sspif is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the ack pulse from the master- receiver is latched on the rising edge of the ninth scl input pulse. if the sda line was high (not ack ), then the data transfer is complete. when the ack is latched by the slave device, the slave logic is reset (resets sspstat register) and the slave device then monitors for another occurrence of the start bit. if the sda line was low (ack ), the transmit data must be loaded into the sspbuf register, which also loads the sspsr reg- ister. then, pin rc3/sck/scl should be enabled by setting bit ckp. table 9-2: data transfer received byte actions status bits as data transfer is received sspsr sspbuf generate ack pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 yes yes yes 10 no no yes 11 no no yes 0 1 no no yes note 1: shaded cells show the conditions where the user software did not properly clear the overflow condition. downloaded from: http:///
pic16f72 ds39597c-page 50 ? 2007 microchip technology inc. figure 9-6: i 2 c waveforms for reception (7-bit address) figure 9-7: i 2 c waveforms for transmission (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read ack receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 0 receiving address sspif (pir1<3>) bf (sspstat<0>) sspov (sspcon<6>) ack ack is not sent. sdascl sspif (pir1<3>) bf (sspstat<0>) ckp (sspcon<4>) a7 a6 a5 a4 a3 a2 a1 ack d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data is sampled scl held low while cpu responds to sspif (the sspbuf must be written to before the ckp bit can be set) downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 51 pic16f72 9.3.2 master mode operation master mode operation is supported in firmware using interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. the stop (p) and start (s) bits will toggle, based on the start and stop conditions. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle and both the s and p bits are clear. in master mode operation, the scl and sda lines are manipulated in firmware by clearing the corresponding trisc<4:3> bit(s). the output level is always low, irre- spective of the value(s) in portc<4:3>. so, when transmitting data, a 1 data bit must have the trisc<4> bit set (input) and a 0 data bit must have the trisc<4> bit cleared (output). the same scenario is true for the scl line with the trisc<3> bit. the following events will cause the ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): ? start condition ? stop condition ? data transfer byte transmitted/received master mode operation can be done with either the slave mode idle (sspm3:sspm0 = 1011 ), or with the slave mode active. when both master mode operation and slave modes are used, the software needs to differentiate the source(s) of the interrupt. for more information on master mode operation, see an554 - software implementation of i 2 c bus master . 9.3.3 multi-master mode operation in multi-master mode operation, the interrupt genera- tion on the detection of the start and stop condi- tions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the ssp module is disabled. the stop (p) and start (s) bits will toggle, based on the start and stop conditions. control of the i 2 c bus may be taken when bit p (sspstat<4>) is set, or the bus is idle and both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master mode operation, the sda line must be monitored to see if the signal level is the expected out- put level. this check only needs to be done when a high level is output. if a high level is expected and a low level is present, the device needs to release the sda and scl lines (set trisc<4:3>). there are two stages where this arbitration can be lost: ? address transfer ? data transfer when the slave logic is enabled, the slave device con- tinues to receive. if arbitration was lost during the address transfer stage, communication to the device may be in progress. if addressed, an ack pulse will be generated. if arbitration was lost during the data trans- fer stage, the device will need to retransfer the data at a later time. for more information on multi-master mode operation, see an578 - use of the ssp module in the i 2 c multi-master environment . table 9-3: registers associated with i 2 c operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh, 8bh, 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 adif s s p i f ccp1if tmr2if tmr1if -0-- 0000 0000 0000 8ch pie1 adie s s p i e ccp1ie tmr2ie tmr1ie -0-- 0000 0000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 94h sspstat smp (1) cke (1) d/a psr / w ua bf 0000 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as 0. shaded cells are not used by ssp module in spi mode. note 1: maintain these bits clear in i 2 c mode. downloaded from: http:///
pic16f72 ds39597c-page 52 ? 2007 microchip technology inc. notes: downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 53 pic16f72 10.0 analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has five inputs for the pic16f72. the a/d allows conversion of an analog input signal to a corresponding 8-bit digital number. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. the analog reference voltage is software selectable to either the devices positive supply voltage (v dd ) or the voltage level on the ra3/an3/v ref pin. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/ds internal rc oscillator. the a/d module has three registers: ? a/d result register adres ? a/d control register 0 adcon0 ? a/d control register 1 adcon1 a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion is aborted. the adcon0 register, shown in register 10-1, con- trols the operation of the a/d module. the adcon1 register, shown in register 10-2, configures the func- tions of the port pins. the port pins can be configured as analog inputs (ra3 can also be a voltage reference) or a digital i/o. for more information on use of the a/d converter, see an546 - use of a/d converter , or refer to the pic? mid-range mcu family reference manual (ds33023). register 10-1: adcon0: a/d control register 0 (address 1fh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done a d o n bit 7 bit 0 bit 7-6 adcs<1:0>: a/d conversion clock select bits 00 =f osc /2 01 =f osc /8 10 =f osc /32 11 =f rc (clock derived from the internal a/d module rc oscillator) bit 5-3 chs<2:0>: analog channel select bits 000 = channel 0, (ra0/an0) 001 = channel 1, (ra1/an1) 010 = channel 2, (ra2/an2) 011 = channel 3, (ra3/an3) 100 = channel 4, (ra5/an4) bit 2 go/done : a/d conversion status bit if adon = 1: 1 = a/d conversion in progress (setting this bit starts the a/d conversion) 0 = a/d conversion not in progress (this bit is automatically cleared by hardware when the a/d conversion is complete) bit 1 unimplemented: read as 0 bit 0 adon: a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shut-off and consumes no operating current legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown downloaded from: http:///
pic16f72 ds39597c-page 54 ? 2007 microchip technology inc. register 10-2: adcon1: a/d control register 1 (address 9fh) the adres register contains the result of the a/d con- version. when the a/d conversion is complete, the result is loaded into the adres register, the go/done bit (adcon0<2>) is cleared, and a/d interrupt flag bit adif is set. the block diagram of the a/d module is shown in figure 10-1. the value in the adres register is not modified for a power-on reset. the adres register will contain unknown data after a power-on reset. after the a/d module has been configured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 10.1. after this acquisition time has elapsed, the a/d conversion can be started. the following steps should be followed for doing an a/d conversion: 1. configure the a/d module: ? configure analog pins/voltage reference and digital i/o (adcon1) ? select a/d input channel (adcon0) ? select a/d conversion clock (adcon0) ? turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): ? clear adif bit ? set adie bit ? set gie bit 3. wait the required acquisition time. 4. start conversion: ? set go/done bit (adcon0) 5. wait for a/d conversion to complete, by either: ? polling for the go/done bit to be cleared or ? waiting for the a/d interrupt 6. read a/d result register (adres), clear bit adif if required. 7. for next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before the next acquisition starts. u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7-3 unimplemented: read as 0 bit 2-0 pcfg<2:0>: a/d port configuration control bits legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown a = analog input d = digital i/o pcfg2:pcfg0 ra0 ra1 ra2 ra5 ra3 v ref 000 aaaaav dd 001 aaaav ref ra3 010 aaaaav dd 011 aaaav ref ra3 100 aaddav dd 101 aaddv ref ra3 11x dddddv dd downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 55 pic16f72 figure 10-1: a/d block diagram figure 10-2: analog input model (input voltage) v ain v ref (reference voltage) v dd pcfg2:pcfg0 chs2:chs0 000 or 010 or 100 001 or 011 or 101 ra5/an4 ra3/an3/v ref ra2/an2 ra1/an1 ra0/an0 100011 010 001 000 a/d converter c pin va rs anx 5 pf v dd v t = 0.6 v v t = 0.6 v i leakage r ic 1 k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v4v 3v 2v 567891011 ( k ) v dd = 51.2 pf 500 na legend: c pin v t i leakage r ic ssc hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions downloaded from: http:///
pic16f72 ds39597c-page 56 ? 2007 microchip technology inc. 10.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 10-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for ana- log sources is 10 k . after the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, t acq , see the pic? mid-range mcu reference manual, (ds33023). in general, however, given a max of 10 k and at a temperature of 100c, t acq will be no more than 16 s. 10.2 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 9.0 t ad per 8-bit conversion. the source of the a/d conversion clock is software selectable. the four possible options for t ad are: ?2t osc ?8t osc ?32t osc ? internal rc oscillator (2 - 6 s) for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time as small as possible, but no less than 1.6 s and not greater than 6.4 s. table 10-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. 10.3 configuring analog port pins the adcon1, and trisa registers control the opera- tion of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs<2:0> bits and the tris bits. 10.4 a/d conversions clearing the go/done bit during a conversion will abort the current conversion. the adres register will not be updated with the partially completed a/d con- version sample. that is, the adres register will con- tinue to contain the value of the last completed conversion (or the last value written to the adres reg- ister). after the a/d conversion is aborted, a 2 t ad wait is required before the next acquisition is started. after this 2 t ad wait, an acquisition is automatically started on the selected channel. the go/done bit can then be set to start the conversion. table 10-1: t ad vs. maximum device operating frequencies (standard devices (c)) note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs, will convert an analog input. analog levels on a digitally configured input will not affect the conversion accuracy. 2: analog levels on any pin that is defined as a digital input (including the an4:an0 pins), may cause the input buffer to consume current out of the device specification. note: the go/done bit should not be set in the same instruction that turns on the a/d. ad clock source (t ad ) maximum device frequency operation adcs<1:0> max. 2 t osc 00 1.25 mhz 8 t osc 01 5 mhz 32 t osc 10 20 mhz rc (1, 2) 11 (note 1) note 1: the rc source has a typical t ad time of 4 s, but can vary between 2-6 s. 2: when the device frequencies are greater than 1 mhz, the rc a/d conversion clock source is only recommended for sleep operation. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 57 pic16f72 10.5 a/d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be set to rc (adcs1:adcs0 = 11 ). when the rc clock source is selected, the a/d module waits one instruction cycle before starting the conversion. this allows the sleep instruction to be executed, which eliminates all digital switching noise from the conversion. when the conver- sion is completed, the go/done bit will be cleared, and the result loaded into the adres register. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d mod- ule will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction will cause the present conver- sion to be aborted and the a/d module to be turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. 10.6 effects of a reset a device reset forces all registers to their reset state. the a/d module is disabled and any conversion in progress is aborted. all a/d input pins are configured as analog inputs. the adres register will contain unknown data after a power-on reset. 10.7 use of the ccp trigger an a/d conversion can be started by the special event trigger of the ccp1 module. this requires that the ccp1m3:ccp1m0 bits (ccp1con<3:0>) be pro- grammed as 1011 and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d conversion, and the timer1 counter will be reset to zero. timer1 is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving the adres to the desired location). the appropriate analog input channel must be selected and the minimum acquisition done before the special event trigger sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), then the special event trigger will be ignored by the a/d module, but will still reset the timer1 counter. table 10-2: registers/bits associated with a/d note: for the a/d module to operate in sleep, the a/d clock source must be set to rc (adcs1:adcs0 = 11 ). to perform an a/d conversion in sleep, ensure the sleep instruction immediately follows the instruction that sets the go/done bit. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 0bh,8bh 10bh,18bh intcon gie peie tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u 0ch pir1 a d i f sspif ccp1if tmr2if tmr1if -0-- 0000 -0-- 0000 8ch pie1 a d i e sspie ccp1ie tmr2ie tmr1ie -0-- 0000 -0-- 0000 1eh adres a/d result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done a d o n 0000 00-0 0000 00-0 9fh adcon1 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 05h porta ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa porta data direction register --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as 0. shaded cells are not used for a/d conversion. downloaded from: http:///
pic16f72 ds39597c-page 58 ? 2007 microchip technology inc. notes: downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 59 pic16f72 11.0 special features of the cpu these devices have a host of features intended to max- imize system reliability, minimize cost through elimina- tion of external components, provide power saving operating modes and offer code protection: ? oscillator selection ? reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) ? interrupts ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming these devices have a watchdog timer, which can be enabled or disabled using a configuration bit. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a fixed delay of 72 ms (nomi- nal) on power-up only. it is designed to keep the part in reset while the power supply stabilizes, and is enabled or disabled using a configuration bit. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up, or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost while the lp crystal option saves power. configuration bits are used to select the desired oscillator mode. additional information on special features is available in the pic? mid-range reference manual (ds33023). 11.1 configuration bits the configuration bits can be programmed (read as 0), or left unprogrammed (read as 1), to select vari- ous device configurations. these bits are mapped in program memory location 2007h. the user will note that address 2007h is beyond the user program memory space, which can be accessed only during programming. downloaded from: http:///
pic16f72 ds39597c-page 60 ? 2007 microchip technology inc. register 11-1: configuration word (address 2007h) (1) u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 u-1 boren c pp w r t e n wdten f0sc1 f0sc0 bit13 bit0 bit 13-7 unimplemented: read as 1 bit 6 boren: brown-out reset enable bit (2) 1 = bor enabled 0 = bor disabled bit 5 unimplemented: read as 1 bit 4 cp: flash program memory code protection bit 1 = code protection off 0 = all memory locations code protected bit 3 pwrten : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 2 wdten: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0 fosc1:fosc0: oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: the erased (unprogrammed) value of the configuration word is 3fffh. 2: enabling brown-out reset automatically enables power-up timer (pwrt), regardless of the value of bit pwrten . ensure the power-up timer is enabled any time brown-out reset is enabled. legend: r = readable bit p = programmable bit u = unimplemented bit, read as 1 - n = value when device is unprogrammed u = unchanged from programmed state downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 61 pic16f72 11.2 oscillator configurations 11.2.1 oscillator types the pic16f72 can be operated in four different oscil- lator modes. the user can program two configuration bits (fosc1 and fosc0) to select one of these four modes: ? lp low power crystal ? xt crystal/resonator ? hs high speed crystal/resonator ? rc resistor/capacitor 11.2.2 crystal oscillator/ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1/clki and osc2/clko pins to establish oscillation (figure 11-1). the pic16f72 oscillator design requires the use of a parallel cut crys- tal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. when in hs mode, the device can accept an external clock source to drive the osc1/clki pin (figure 11-2). see figure 14-1 or figure 14-2 (depending on the part number and v dd range) for valid external clock frequencies. figure 11-1: crystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 11-2: external clock input operation (hs osc configuration) table 11-1: ceramic resonators (for design guidance only) note 1: see table 11-1 and table 11-2 for typical values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen. c1 (1) c2(1) xtal osc2 osc1 rf(3) sleep to logic pic16f72 rs (2) internal typical capacitor values used: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 56 pf 47 pf 33 pf 56 pf 47 pf 33 pf hs 8.0 mhz 16.0 mhz 27 pf 22 pf 27 pf 22 pf capacitor values are for design guidance only. these capacitors were tested with the resonators listed below for basic start-up and operation. these values were not optimized. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. see the notes at the bottom of page 62 for additional information. osc1 osc2 open clock from ext. system pic16f72 (hs mode) downloaded from: http:///
pic16f72 ds39597c-page 62 ? 2007 microchip technology inc. table 11-2: capacitor selection for crystal oscillator (for design guidance only) 11.2.3 rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values, and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c com- ponents used. figure 11-3 shows how the r/c combination is connected to the pic16f72. figure 11-3: rc oscillator mode 11.3 reset the pic16f72 differentiates between various kinds of reset: ? power-on reset (por) ?mclr reset during normal operation ?mclr reset during sleep ? wdt reset (during normal operation) ? wdt wake-up (during sleep) ? brown-out reset (bor) some registers are not affected in any reset condi- tion. their status is unknown on por and unchanged in any other reset. most other registers are reset to a reset state on power-on reset (por), on the mclr and wdt reset, on mclr reset during sleep, and brown-out reset (bor). they are not affected by a wdt wake-up, which is viewed as the resumption of normal operation. the to and pd bits are set or cleared differently in different reset situa- tions, as indicated in table 11-4. these bits are used in software to determine the nature of the reset. see table 11-6 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 11-4. osc type crystal freq typical capacitor values tested: c1 c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 56 pf 56 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15 pf 15 pf 20 mhz 15 pf 15 pf capacitor values are for design guidance only. these capacitors were tested with the crystals listed below for basic start-up and operation. these values were not optimized. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. see the notes following this table for additional information. note 1: higher capacitance increases the stability of oscillator, but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appro- priate values of external components. 3: rs may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specification. 4: always verify oscillator performance over the v dd and temperature range that is expected for the application. osc2/clko c ext r ext pic16f72 osc1 f osc /4 internal clock v dd v ss recommended values: 3 k r ext 100 k c ext > 20 pf downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 63 pic16f72 figure 11-4: simplified block diagram of on-chip reset circuit 11.4 mclr pic16f72 device has a noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. the behavior of the esd protection on the mclr pin has been altered from previous devices of this family. voltages applied to the pin that exceed its specification can result in both mclr and excessive current beyond the device specification during the esd event. for this reason, microchip recommends that the mclr pin no longer be tied directly to v dd . the use of an rc network, as shown in figure 11-5, is suggested. figure 11-5: recommended mclr circuit s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt on-chip rc osc wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost enable pwrt sleep note 1: this is a separate oscillator from the rc oscillator of the clki pin. brown-out reset boren (1) c1 0.1 f r11 k (or greater) (optional, not critical) v dd mclr pic16f72 downloaded from: http:///
pic16f72 ds39597c-page 64 ? 2007 microchip technology inc. 11.5 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.2v - 1.7v). to take advantage of the por, tie the mclr pin to v dd , as described in section 11.4. a maximum rise time for v dd is specified. see section 14.0, electrical characteristics for details. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. for more information, see application note, an607- power-up trouble shooting (ds00607). 11.6 power-up timer (pwrt) the power-up timer provides a fixed 72 ms nominal time-out on power-up only from the por. the power- up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrts time delay allows v dd to rise to an accept- able level. a configuration bit is provided to enable/ disable the pwrt. the power-up time delay will vary from chip to chip due to v dd , temperature and process variation. see dc parameters for details (t pwrt , parameter #33). 11.7 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides 1024 oscillator cycles (from osc1 input) delay after the pwrt delay is over (if enabled). this helps to ensure that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on power-on reset or wake-up from sleep. 11.8 brown-out reset (bor) the configuration bit, boren, can enable or disable the brown-out reset circuit. if v dd falls below v bor (parameter d005, about 4v) for longer than t bor (parameter #35, about 100 s), the brown-out situation will reset the device. if v dd falls below v bor for less than t bor , a reset may not occur. once the brown-out occurs, the device will remain in brown-out reset until v dd rises above v bor . the power-up timer then keeps the device in reset for t pwrt (parameter #33, about 72 ms). if v dd should fall below v bor during t pwrt , the brown-out reset pro- cess will restart when v dd rises above v bor , with the power-up timer reset. the power-up timer is always enabled when the brown-out reset circuit is enabled, regardless of the state of the pwrt configuration bit. 11.9 time-out sequence on power-up, the time-out sequence is as follows: the pwrt delay starts (if enabled) when a por occurs. then, ost starts counting 1024 oscillator cycles when pwrt ends (lp, xt, hs). when the ost ends, the device comes out of reset. if mclr is kept low long enough, all delays will expire. bringing mclr high will begin execution immediately. this is useful for testing purposes or to synchronize more than one pic16f72 device operating in parallel. table 11-5 shows the reset conditions for the status, pcon and pc registers, while table 11-6 shows the reset conditions for all the registers. 11.10 power control/status register (pcon) the power control/status register, pcon, has two bits to indicate the type of reset that last occurred. bit0 is brown-out reset status bit, bor . bit bor is unknown on a power-on reset. it must then be set by the user and checked on subsequent resets to see if bit bor cleared, indicating a brown-out reset occurred. when the brown-out reset is disabled, the state of the bor bit is unpredictable. bit1 is por (power-on reset status bit). it is cleared on a power-on reset and unaffected otherwise. the user must set this bit following a power-on reset. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 65 pic16f72 table 11-3: time-out in various situations table 11-4: status bits and their significance table 11-5: reset condition for special registers oscillator configuration power-up brown-out wake-up from sleep pwrten = 0 pwrten = 1 xt, hs, lp 72 ms + 1024 t osc 1024 t osc 72 ms + 1024 t osc 1024 t osc rc 72 ms 72 ms por (pcon<1>) bor (pcon<0>) to (status<4>) pd (status<3>) significance 0x 1 1 power-on reset 0x 0 x illegal, to is set on por 0x x 0 illegal, pd is set on por u0 1 1 brown-out reset uu 0 1 wdt reset uu 0 0 wdt wake-up uu u u mclr reset during normal operation uu 1 0 mclr reset during sleep or interrupt wake-up from sleep condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 0001 1uuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'. note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). downloaded from: http:///
pic16f72 ds39597c-page 66 ? 2007 microchip technology inc. table 11-6: initialization conditions for all registers register power-on reset, brown-out reset mclr reset, wdt reset wake-up via wdt or interrupt w xxxx xxxx uuuu uuuu uuuu uuuu indf n/a n/a n/a tmr0 xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000h 0000h pc + 1 (2) status 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr xxxx xxxx uuuu uuuu uuuu uuuu porta --0x 0000 --0u 0000 --uu uuuu portb xxxx xxxx uuuu uuuu uuuu uuuu portc xxxx xxxx uuuu uuuu uuuu uuuu pclath ---0 0000 ---0 0000 ---u uuuu intcon 0000 000x 0000 000u uuuu uuuu (1) pir1 -0-- 0000 -0-- 0000 -u-- uuuu (1) tmr1l xxxx xxxx uuuu uuuu uuuu uuuu tmr1h xxxx xxxx uuuu uuuu uuuu uuuu t1con --00 0000 --uu uuuu --uu uuuu tmr2 0000 0000 0000 0000 uuuu uuuu t2con -000 0000 -000 0000 -uuu uuuu sspbuf xxxx xxxx uuuu uuuu uuuu uuuu sspcon 0000 0000 0000 0000 uuuu uuuu ccpr1l xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h xxxx xxxx uuuu uuuu uuuu uuuu ccp1con --00 0000 --00 0000 --uu uuuu adres xxxx xxxx uuuu uuuu uuuu uuuu adcon0 0000 00-0 0000 00-0 uuuu uu-u option 1111 1111 1111 1111 uuuu uuuu trisa --11 1111 --11 1111 --uu uuuu trisb 1111 1111 1111 1111 uuuu uuuu trisc 1111 1111 1111 1111 uuuu uuuu pie1 -0-- 0000 -0-- 0000 -u-- uuuu pcon ---- --qq ---- --uu ---- --uu pr2 1111 1111 1111 1111 1111 1111 sspadd 0000 0000 0000 0000 uuuu uuuu sspstat --00 0000 --00 0000 --uu uuuu adcon1 ---- -000 ---- -000 ---- -uuu pmdatl 0--- 0000 0--- 0000 u--- uuuu pmadrl xxxx xxxx uuuu uuuu uuuu uuuu pmdath xxxx xxxx uuuu uuuu uuuu uuuu pmadrh xxxx xxxx uuuu uuuu uuuu uuuu pmcon1 1--- ---0 1--- ---0 1--- ---u legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved, maintain clear. note 1: one or more bits in intcon, pir1 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 11-5 for reset value for specific condition. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 67 pic16f72 figure 11-6: time-out sequence on power-up (mclr tied to v dd through pull-up resistor) figure 11-7: time-out sequence on power-up (mclr tied to v dd through rc network): case 1 figure 11-8: time-out sequence on power-up (mclr tied to v dd through rc network): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost downloaded from: http:///
pic16f72 ds39597c-page 68 ? 2007 microchip technology inc. figure 11-9: slow rise time (mclr tied to v dd through rc network) 11.11 interrupts the pic16f72 has up to eight sources of interrupt. the interrupt control register (intcon) records individual interrupt requests in flag bits. it also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. when bit gie is enabled, and an interrupts flag bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be dis- abled through their corresponding enable bits in vari- ous registers. individual interrupt bits are set, regardless of the status of the gie bit. the gie bit is cleared on reset. the return from interrupt instruction, retfie , exits the interrupt routine, as well as sets the gie bit, which re-enables interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. the peripheral interrupt flags are contained in the special function register, pir1. the corresponding interrupt enable bits are contained in special function register, pie1, and the peripheral interrupt enable bit is contained in special function register intcon. when an interrupt is serviced, the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack, and the pc is loaded with 0004h. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs, relative to the current q cycle. the latency is the same for one or two cycle instructions. individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, peie bit, or the gie bit. figure 11-10: interrupt logic v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost note: individual interrupt flag bits are set, regard- less of the status of their corresponding mask bit, or the gie bit. adif adie sspif sspie ccp1if ccp1ie tmr2if tmr2ie tmr1if tmr1ie tmr0if tmr0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 69 pic16f72 11.11.1 int interrupt external interrupt on the rb0/int pin is edge triggered, either rising, if bit intedg (option<6>) is set, or fall- ing, if the intedg bit is clear. when a valid edge appears on the rb0/int pin, flag bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service routine before re-enabling this interrupt. the int inter- rupt can wake-up the processor from sleep, if bit inte was set prior to going into sleep. the status of global interrupt enable bit gie decides whether or not the processor branches to the interrupt vector following wake-up. see section 11.14 for details on sleep mode. 11.11.2 tmr0 interrupt an overflow (ffh 00h) in the tmr0 register will set flag bit tmr0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit tmr0ie (intcon<5>) (see section 4.0). 11.11.3 portb intcon change an input change on portb<7:4> sets flag bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit rbie (intcon<4>) (see section 3.2). 11.12 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt (i.e., w, status registers). this will have to be implemented in software, as shown in example 11-1. for the pic16f72 device, the register w_temp must be defined in both banks 0 and 1 and must be defined at the same offset from the bank base address (i.e., if w_temp is defined at 20h in bank 0, it must also be defined at a0h in bank 1). the register status_temp is only defined in bank 0. example 11-1: saving status, w and pclath registers in ram movwf w_temp ;copy w to temp register swapf status,w ;swap status to be saved into w clrf status ;bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ;save status to bank zero status_temp register : :(isr) ;insert user code here : swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w downloaded from: http:///
pic16f72 ds39597c-page 70 ? 2007 microchip technology inc. 11.13 watchdog timer (wdt) the watchdog timer is a free running, on-chip rc oscillator that does not require any external compo- nents. this rc oscillator is separate from the rc oscil- lator of the osc1/clki pin. that means that the wdt will run, even if the clock on the osc1/clki and osc2/ clko pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watchdog timer wake-up). the to bit in the status register will be cleared upon a watchdog timer time-out. the wdt can be permanently disabled by clearing configuration bit wdten (see section 11.1). wdt time-out period values may be found in the elec- trical specifications section under parameter #31. val- ues for the wdt prescaler (actually a postscaler, but shared with the timer0 prescaler) may be assigned using the option register. figure 11-11: watchdog timer block diagram table 11-7: summary of watchdog timer registers note 1: the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and prevent it from timing out and generating a device reset condition. 2: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared, but the prescaler assignment is not changed. from tmr0 clock source (figure 4-1) to t m r 0 ( f i g u r e 4 - 1 ) postscaler wdt timer wdt enable bit 01 mu x psa 8 - to - 1 mux ps2:ps0 0 1 mux psa wdt time-out note: psa and ps2:ps0 are bits in the option register. 8 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h config. bits (1) boren (1) cp pwrten (1) wdten fosc1 fosc0 81h,181h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer. note 1: see register 11-1 for operation of these bits. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 71 pic16f72 11.14 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (status<3>) is cleared, the to (status<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, low, or hi-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d and disable external clocks. pull all i/o pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should also be considered. the mclr pin must be at a logic high level (v ihmc ). 11.14.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change or a peripheral interrupt. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a "wake-up". the to and pd bits in the status register can be used to determine the cause of the device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred and caused wake-up. the following peripheral interrupts can wake the device from sleep: 1. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 2. ccp capture mode interrupt. 3. special event trigger (timer1 in asynchronous mode using an external clock). 4. ssp (start/stop) bit detect interrupt. 5. ssp transmit or receive in slave mode (spi/i 2 c). 6. a/d conversion (when a/d clock source is rc). other peripherals cannot generate interrupts since during sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up occurs regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the interrupt address (0004h). in cases where the execu- tion of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 11.14.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will com- plete as a nop . therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. ? if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will imme- diately wake-up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruction should be executed before a sleep instruction. downloaded from: http:///
pic16f72 ds39597c-page 72 ? 2007 microchip technology inc. figure 11-12: wake-up from sleep through interrupt 11.15 program verification/ code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 11.16 id locations four memory locations (2000h - 2003h) are designated as id locations, where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution, but are read- able and writable during program/verify. it is recom- mended that only the four least significant bits of the id location are used. 11.17 in-circuit serial programming pic16f72 microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage (see figure 11-13 for an example). this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. for general information of serial programming, please refer to the in-circuit serial programming? (icsp?) guide (ds30277). for specific details on programming commands and operations for the pic16f72 devices, please refer to the latest version of the pic16f72 flash program memory programming specification (ds39588). figure 11-13: typical in-circuit serial programming connection q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clko (4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024 t osc (drawing not to scale) this delay will not be there for rc osc mode. 3: gie = 1' assumed. in this case, after wake-up, the processor jumps to the interrupt routine. if gie = 0', execution will continue in-line. 4: clko is not available in these osc modes, but shown here for timing reference. external connector signals to n o rm a l connections to n o rm a l connections pic16f72 v dd v ss mclr /v pp rb6 rb7 +5v 0v v pp clk data i/o v dd * * * * * isolation devices (as required). downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 73 pic16f72 12.0 instruction set summary each pic16f72 instruction is a 14-bit word divided into an opcode that specifies the instruction type and one or more operands that further specify the operation of the instruction. the pic16f72 instruction set summary in table 12-2 lists byte-oriented , bit-oriented , and lit- eral and control operations. table 12-1 shows the opcode field descriptions. for byte-oriented instructions, f represents a file reg- ister designator and d represents a destination desig- nator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if d is zero, the result is placed in the w register. if d is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, b represents a bit field designator which selects the number of the bit affected by the operation, while f represents the number of the file in which the bit is located. for literal and control operations, k represents an eight or eleven-bit constant or literal value. table 12-1: opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles, with the second cycle executed as a nop . one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. table 12-2 lists the instructions recognized by the mpasm tm assembler. figure 12-1 shows the general formats that the instructions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. figure 12-1: general format for instructions a description of each instruction is available in the pic? mid-range mcu family reference manual (ds33023). field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1). the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in file register f. default is d = 1. pc program counter to time-out bit pd power-down bit byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only downloaded from: http:///
pic16f72 ds39597c-page 74 ? 2007 microchip technology inc. table 12-2: pic16f72 instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 11 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 0000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfffdfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffffffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 11 1 (2) 1 (2) 0101 01 01 00bb 01bb 10bb 11bb bfffbfff bfff bfff ffffffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw kk k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 11 2 1 2 1 1 2 2 2 1 1 1 11 1110 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkkkkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkkkkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to , pd zto , pd c,dc,z z note 1: when an i/o register is modified as a function of itself (e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data will be written back with a 0. 2: if this instruction is executed on the tmr0 register (and where applicable, d = 1), the pr escaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is m odified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . note: additional information on the mid-range instruction set is available in the pic? mid-range mcu family reference manual (ds33023). downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 75 pic16f72 12.1 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k (w) status affected: c, dc, z description: the contents of the w register are added to the eight-bit literal k and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d [0,1] operation: (w) + (f) (destination) status affected: c, dc, z description: add the contents of the w register with register f. if d = 0, the result is stored in the w register. if d = 1, the result is stored back in register f. andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) (w) status affected: z description: the contents of w register are anded with the eight-bit literal k. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d [0,1] operation: (w) .and. (f) (destination) status affected: z description: and the w register with register f. if d = 0, the result is stored in the w register. if d = 1, the result is stored back in register f. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 (f) status affected: none description: bit b in register f is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 (f) status affected: none description: bit b in register f is set. downloaded from: http:///
pic16f72 ds39597c-page 76 ? 2007 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit b in register f = 0, the next instruction is executed. if bit b = 1, then the next instruc- tion is discarded and a nop is exe- cuted instead, making this a 2 t cy instruction. btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit b in register f = 1, the next instruction is executed. if bit b in register f = 0, the next instruction is discarded, and a nop is executed instead, making this a 2 t cy instruction. call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc) + 1 tos, k pc<10:0>, (pclath<4:3>) pc<12:11> status affected: none description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven-bit immedi- ate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h (f) 1 z status affected: z description: the contents of register f are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w) 1 z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt 0 wdt prescaler, 1 to 1 pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 77 pic16f72 comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d [0,1] operation: (f) (destination) status affected: z description: the contents of register f are complemented. if d = 0, the result is stored in w. if d = 1, the result is stored back in register f. decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination) status affected: z description: decrement register f. if d = 0, the result is stored in the w register. if d = 1, the result is stored back in register f. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination); skip if result = 0 status affected: none description: the contents of register f are decremented. if d = 0, the result is placed in the w register. if d = 1, the result is placed back in register f. if the result is 1, the next instruc- tion is executed. if the result is 0, then a nop is executed instead, making it a 2 t cy instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k pc<10:0> pclath<4:3> pc<12:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two-cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination) status affected: z description: the contents of register f are incremented. if d = 0, the result is placed in the w register. if d = 1, the result is placed back in register f. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination), skip if result = 0 status affected: none description: the contents of register f are incremented. if d = 0, the result is placed in the w register. if d = 1, the result is placed back in register f. if the result is 1, the next instruc- tion is executed. if the result is 0, a nop is executed instead, making it a 2 t cy instruction. downloaded from: http:///
pic16f72 ds39597c-page 78 ? 2007 microchip technology inc. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k (w) status affected: z description: the contents of the w register are ord with the eight-bit literal k. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d [0,1] operation: (w) .or. (f) (destination) status affected: z description: inclusive or the w register with register f. if d = 0, the result is placed in the w register. if d = 1, the result is placed back in register f. movf move f syntax: [ label ] movf f,d operands: 0 f 127 d [0,1] operation: (f) (destination) status affected: z description: the contents of register f are moved to a destination dependant upon the status of d. if d = 0, the destination is w register. if d = 1, the destination is file reg- ister f itself. d = 1 is useful to test a file register, since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none description: the eight-bit literal k is loaded into w register. the dont cares will assemble as 0s. movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) (f) status affected: none description: move data from w register to register f. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 79 pic16f72 retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos pc, 1 gie status affected: none retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none description: the w register is loaded with the eight-bit literal k. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. return return from subroutine syntax: [ label ] return operands: none operation: tos pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register f are rotated one bit to the left through the carry flag. if d = 0, the result is placed in the w register. if d = 1, the result is stored back in register f. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c description: the contents of register f are rotated one bit to the right through the carry flag. if d = 0, the result is placed in the w register. if d = 1, the result is placed back in register f. sleep syntax: [ label ]sleep operands: none operation: 00h wdt, 0 wdt prescaler, 1 to , 0 pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. register f c register f c downloaded from: http:///
pic16f72 ds39597c-page 80 ? 2007 microchip technology inc. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ( w) status affected: c, dc, z description: the w register is subtracted (2s complement method) from the eight-bit literal k. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d [0,1] operation: (f) - (w) ( destination) status affected: c, dc, z description: subtract (2s complement method) w register from register f. if d = 0, the result is stored in the w register. if d = 1, the result is stored back in register f. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d [0,1] operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) status affected: none description: the upper and lower nibbles of register f are exchanged. if d = 0, the result is placed in w register. if d = 1, the result is placed in register f. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z description: the contents of the w register are xored with the eight-bit literal k. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d [0,1] operation: (w) .xor. (f) ( destination) status affected: z description: exclusive or the contents of the w register with register f. if d = 0, the result is stored in the w register. if d = 1, the result is stored back in register f. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 81 pic16f72 13.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - icepic? in-circuit emulator ? in-circuit debugger - mplab icd ? device programmers -pro mate ? ii universal device programmer - picstart ? plus entry-level development programmer ? low cost demonstration boards - picdem tm 1 demonstration board - picdem 2 demonstration board - picdem 3 demonstration board - picdem 17 demonstration board -k ee l oq ? demonstration board 13.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. the mplab ide is a windows ? -based application that contains: ? an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor ? a project manager ? customizable toolbar and key mapping ? a status bar ? on-line help the mplab ide allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to pic emulator and simulator tools (automatically updates all project information) ? debug using: - source files - absolute listing file - machine code the ability to use mplab ide with multiple debugging tools allows users to easily switch from the cost- effective simulator to a full-featured emulator with minimal retraining. 13.2 mpasm assembler the mpasm assembler is a full-featured universal macro assembler for all pic mcus. the mpasm assembler has a command line interface and a windows shell. it can be used as a stand-alone application on a windows 3.x or greater system, or it can be used through mplab ide. the mpasm assem- bler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, an abso- lute lst file that contains source lines and generated machine code, and a cod file for debugging. the mpasm assembler features include: ? integration into mplab ide projects. ? user-defined macros to streamline assembly code. ? conditional assembly for multi-purpose source files. ? directives that allow complete control over the assembly process. 13.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi c compilers for microchips pic17cxxx and pic18cxxx family of microcontrollers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display. downloaded from: http:///
pic16f72 ds39597c-page 82 ? 2007 microchip technology inc. 13.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can also link relocatable objects from pre-compiled libraries, using directives from a linker script. the mplib object librarian is a librarian for pre- compiled code to be used with the mplink object linker. when a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the mplib object librarian manages the creation and modification of library files. the mplink object linker features include: ? integration with mpasm assembler and mplab c17 and mplab c18 c compilers. ? allows all memory areas to be defined as sections to provide link-time flexibility. the mplib object librarian features include: ? easier linking because single libraries can be included instead of many smaller files. ? helps keep code maintainable by grouping related modules together. ? allows libraries to be created and modules to be added, listed, replaced, deleted or extracted. 13.5 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc-hosted environment by simulating the pic series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. the execu- tion can be performed in single step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debug- ging using the mplab c17 and the mplab c18 c com- pilers and the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi- project software development tool. 13.6 mplab ice high performance universal in-circuit emulator with mplab ide the mplab ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic micro- controllers (mcus). software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment (ide), which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. the pc platform and microsoft ? windows environment were chosen to best make these features available to you, the end user. 13.7 icepic in-circuit emulator the icepic low cost, in-circuit emulator is a solution for the microchip technology pic16c5x, pic16c6x, pic16c7x and pic16cxxx families of 8-bit one- time-programmable (otp) microcontrollers. the mod- ular system can support different subsets of pic16c5x or pic16cxxx products through the use of inter- changeable personality modules, or daughter boards. the emulator is capable of emulating without target application circuitry being present. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 83 pic16f72 13.8 mplab icd in-circuit debugger microchip's in-circuit debugger, mplab icd, is a pow- erful, low cost, run-time development tool. this tool is based on the flash pic mcus and can be used to develop for this and other pic microcontrollers. the mplab icd utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip's in-circuit serial programming tm protocol, offers cost-effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. running at full speed enables testing hardware in real-time. 13.9 pro mate ii universal device programmer the pro mate ii universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as pc-hosted mode. the pro mate ii device programmer is ce compliant. the pro mate ii device programmer has program- mable v dd and v pp supplies, which allow it to verify programmed memory at v dd min and v dd max for max- imum reliability. it has an lcd display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, or program pic devices. it can also set code protection in this mode. 13.10 picstart plus entry level development programmer the picstart plus development programmer is an easy-to-use, low cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer sup- ports all pic devices with up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 13.11 picdem 1 low cost pic demonstration board the picdem 1 demonstration board is a simple board which demonstrates the capabilities of several of microchips microcontrollers. the microcontrollers sup- ported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the user can program the sample microcon- trollers provided with the picdem 1 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the user can also connect the picdem 1 demonstration board to the mplab ice in- circuit emulator and download the firmware to the emu- lator for testing. a prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simu- lated analog input, push button switches and eight leds connected to portb. 13.12 picdem 2 low cost pic16cxx demonstration board the picdem 2 demonstration board is a simple dem- onstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and soft- ware is included to run the basic demonstration pro- grams. the user can program the sample microcontrollers provided with the picdem 2 demon- stration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 2 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding additional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a serial eeprom to demonstrate usage of the i 2 c tm bus and separate headers for connection to an lcd module and a keypad. downloaded from: http:///
pic16f72 ds39597c-page 84 ? 2007 microchip technology inc. 13.13 picdem 3 low cost pic16cxxx demonstration board the picdem 3 demonstration board is a simple dem- onstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with an lcd mod- ule. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers pro- vided with the picdem 3 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer with an adapter socket, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 3 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem 3 demonstration board is a lcd panel, with 4 commons and 12 segments, that is capable of display- ing time, temperature and day of the week. the picdem 3 demonstration board provides an additional rs-232 interface and windows software for showing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hardware demultiplexer for the lcd signals. 13.14 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. all neces- sary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. a programmed sample is included and the user may erase it and program it with the other sample programs using the pro mate ii device programmer, or the picstart plus development programmer, and easily debug and test the sample code. in addition, the picdem 17 dem- onstration board supports downloading of programs to and executing out of external flash memory on board. the picdem 17 demonstration board is also usable with the mplab ice in-circuit emulator, or the picmaster emulator and all of the sample programs can be run and modified using either emulator. addition- ally, a generous prototype area is available for user hardware. 13.15 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes a lcd display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 85 pic16f72 table 13-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x/ pic16f8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 pic18fxxx 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment 999999999999999 mplab ? c17 c compiler 99 mplab ? c18 c compiler 99 mpasm tm assembler/ mplink tm object linker 999999999999999 9 9 emulators mplab ? ice in-circuit emulator 999 9 99 ** 999999999 icepic tm in-circuit emulator 9 999 999 9 debugger mplab ? icd in-circuit debugger 9 * 9 * 99 programmers picstart ? plus entry level development programmer 999 9 99 ** 999999999 pro mate ? ii universal device programmer 999 9 99 ** 999999999 9 9 demo boards and eval kits picdem tm 1 demonstration board 999 ? 99 picdem tm 2 demonstration board 9 ? 9 ? 99 picdem tm 3 demonstration board 9 picdem tm 14a demonstration board 9 picdem tm 17 demonstration board 9 k ee l oq ? evaluation kit 9 k ee l oq ? transponder kit 9 microid tm programmers kit 9 125 khz microid tm developers kit 9 125 khz anticollision microid tm developers kit 9 13.56 mhz anticollision microid tm developers kit 9 mcp2510 can developers kit 9 * contact the microchip technology inc. web site at www.microchip.com for information on how to u se the mplab ? icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77. ** contact microchip technology inc. for availability date. ? development tool is available on select devices. downloaded from: http:///
pic16f72 ds39597c-page 86 ? 2007 microchip technology inc. notes: downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 87 pic16f72 14.0 electrical characteristics absolute maximum ratings ? ambient temperature under bias................................................................................................. ............... -55 to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr . and ra4) ......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ............................................................................................................ -0.3 to +6.5v voltage on mclr with respect to v ss (note 2) ..............................................................................................0 to +13.5v voltage on ra4 with respect to vss ............................................................................................. ......................0 to +12v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin ....................................................................................................25 ma maximum current sunk by porta, portb..........................................................................................................200 ma maximum current sourced by porta, portb ........................................................................................ ............200 ma maximum current sunk by portc .................................................................................................. .....................200 ma maximum current sourced by portc ............................................................................................... ...................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd - v oh ) x i oh } + (v o l x i ol ) 2: voltage spikes at the mclr pin may cause unpredictable results. a series resistor of greater than 1 k should be used to pull mclr to v dd , rather than tying the pin directly to v dd . ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the devi ce at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. downloaded from: http:///
pic16f72 ds39597c-page 88 ? 2007 microchip technology inc. figure 14-1: pic16f72 (industrial, extended) voltage-frequency graph figure 14-2: pic16lf72 (industrial) voltage-frequency graph frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 20 mhz 5.0v 3.5v 3.0v 2.5v 16 mhz frequency voltage 6.0v5.5v 4.5v 4.0v 2.0v 5.0v3.5v 3.0v 2.5v f max = (12 mhz/v) (v ddappmin - 2.5v) + 4 mhz note 1: v ddappmin is the minimum voltage of the pic ? device in the application. 4 mhz 10 mhz note 2: f max has a maximum frequency of 10 mhz. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 89 pic16f72 14.1 dc characteristics: pic16f72 (industrial, extended) pic16lf72 (industrial) pic16lf72 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f72 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions v dd supply voltage d001 pic16lf72 2.0 2.52.2 5.5 5.5 5.5 vv v a/d not used, -40c to +85c a/d in use, -40c to +85c a/d in use, 0c to +85c d001 d001a pic16f72 4.0 v bor * 5.5 5.5 vv all configurations bor enabled (note 7) d002* v dr ram data retention voltage (note 1) 1 . 5v d003 v por v dd start voltage to ensure internal power-on reset signal v ss v see section on power-on reset for details d004* sv dd v dd rise rate to ensure internal power-on reset signal 0.05 v/ms see section on power-on reset for details d005 v bor brown-out reset voltage 3.65 4.0 4.35 v boren bit in configuration word enabled * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidan ce only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k . 5: timer1 oscillator (when enabled) adds approximately 20 a to the specification. this value is from characterization and is for design guidance only. this is not tested. 6: the current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached. downloaded from: http:///
pic16f72 ds39597c-page 90 ? 2007 microchip technology inc. i dd supply current (notes 2, 5) d010 d010a pic16lf72 0.4 25 2.0 48 ma a xt, rc osc configuration f osc = 4 mhz, v dd = 3.0v (note 4) lp osc configuration f osc = 32 khz, v dd = 3.0v, wdt disabled d010 d013 pic16f72 - 0.95.2 4 15 mama xt, rc osc configuration f osc = 4 mhz, v dd = 5.5v (note 4) hs osc configuration f osc = 20 mhz, v dd = 5.5v d015* i bor brown-out reset current (note 6) 25 200 a bor enabled, v dd = 5.0v i pd power-down current (notes 3, 5) d020 d021 pic16lf72 2.00.1 30 5 a a v dd = 3.0v, wdt enabled, -40 c to +85 c v dd = 3.0v, wdt disabled, -40 c to +85 c d020 d021 pic16f72 5.00.1 4219 a a v dd = 4.0v, wdt enabled, -40 c to +85 c v dd = 4.0v, wdt disabled, -40 c to +85 c d023* i bor brown-out reset current (note 6) 25 200 a bor enabled, v dd = 5.0v 14.1 dc characteristics: pic16f72 (industrial, extended) pic16lf72 (industrial) (continued) pic16lf72 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic16f72 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidan ce only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss . 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k . 5: timer1 oscillator (when enabled) adds approximately 20 a to the specification. this value is from characterization and is for design guidance only. this is not tested. 6: the current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement. 7: when bor is enabled, the device will operate correctly until the v bor voltage trip point is reached. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 91 pic16f72 14.2 dc characteristics: pic16f72 (industrial, extended) pic16lf72 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc specification, section 14.1. param no. sym characteristic min typ? max units conditions v il input low voltage i/o ports d030 with ttl buffer v ss 0.15 v dd v for entire v dd range d030a v ss 0 . 8 v v4 . 5 v v dd 5.5v d031 with schmitt trigger buffer v ss 0.2 v dd v d032 mclr , osc1 (in rc mode) v ss 0.2 v dd v d033 osc1 (in xt and lp mode) v ss 0 . 3 v v (note 1) osc1 (in hs mode) v ss 0.3 v dd v (note 1) v ih input high voltage i/o ports d040 with ttl buffer 2.0 v dd v4.5v v dd 5.5v d040a 0.25 v dd + 0.8v v dd v for entire v dd range d041 with schmitt trigger buffer 0.8 v dd v dd v for entire v dd range d042 mclr 0.8 v dd v dd v d042a osc1 (in xt and lp mode) 1.6v v dd v (note 1) osc1 (in hs mode) 0.7 v dd v dd v (note 1) d043 osc1 (in rc mode) 0.9 v dd v dd v d070 i purb portb weak pull-up current 50 250 400 av dd = 5v, v pin = v ss i il input leakage current (notes 2, 3) d060 i/o ports 1 avss v pin v dd , pin at hi-impedance d061 mclr , ra4/t0cki 5 avss v pin v dd d063 osc1 5 avss v pin v dd , xt, hs and lp osc configuration * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for desi gn guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the pic16f72 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages . 3: negative current is defined as current sourced by the pin. downloaded from: http:///
pic16f72 ds39597c-page 92 ? 2007 microchip technology inc. v ol output low voltage d080 i/o ports 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d083 osc2/clko (rc osc config) 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c v oh output high voltage d090 i/o ports (note 3) v dd - 0.7 v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d092 osc2/clko (rc osc config) v dd - 0.7 v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d150* v od open drain high voltage 1 2v r a 4 p i n capacitive loading specs on output pins d100 c osc2 osc2 pin 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101 c io all i/o pins and osc2 (in rc mode) 50 pf d102 c b scl, sda in i 2 c mode 4 0 0p f program flash memory d130 e p endurance 100 1000 e/w 25 c at 5v d131 v pr v dd for read 2.0 5.5 v 14.2 dc characteristics: pic16f72 (industrial, extended) pic16lf72 (industrial) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc specification, section 14.1. param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for desi gn guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the pic16f72 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages . 3: negative current is defined as current sourced by the pin. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 93 pic16f72 14.3 timing parameter symbology the timing parameter symbols have been created following one of the following formats: figure 14-3: load conditions 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clko rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ff a l l pp e r i o d hh i g h rr i s e i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 load condition 2 downloaded from: http:///
pic16f72 ds39597c-page 94 ? 2007 microchip technology inc. figure 14-4: external clock timing table 14-1: external clock timing requirements osc1 clko q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 parameter no. symbol characteristic min typ? max units conditions f osc external clki frequency (note 1) dc 1 mhz xt osc mode dc 20 mhz hs osc mode dc 32 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 45 20 200 mhz khz hs osc mode lp osc mode 1 t osc external clki period (note 1) 1000 ns xt osc mode 50 ns hs osc mode 5 ms lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 50 250 ns hs osc mode 5m s l p o s c m o d e 2 t cy instruction cycle time (note 1) 200 t cy dc ns t cy = 4/f osc 3 to sl , to sh external clock in (osc1) high or low time 500 ns xt oscillator 2.5 ms lp oscillator 15 ns hs oscillator 4 to sr , to sf external clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator opera tion and/or higher than expected current consumption. all devices are tested to operate at "min" values with an external clock applied to the osc1/clki pin. when an external clock input is used, the "max" cycl e time limit is "dc" (no clock) for all devices. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 95 pic16f72 figure 14-5: clko and i/o timing table 14-2: clko and i/o timing requirements note: refer to figure 14-3 for load conditions. osc1 clko i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value param no. symbol characteristic min typ? max units conditions 10* tosh2ckl osc1 to clko 75 200 ns (note 1) 11* tosh2ckh osc1 to clko 75 200 ns (note 1) 12* tckr clko rise time 35 100 ns (note 1) 13* tckf clko fall time 35 100 ns (note 1) 14* tckl2iov clko to port out valid 0.5 t cy + 20 ns (note 1) 15* tiov2ckh port in valid before clko t osc + 200 ns (note 1) 16* tckh2ioi port in hold after clko 0n s (note 1) 17* tosh2iov osc1 (q1 cycle) to port out valid 100 255 ns 18* tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) standard ( f ) 100 ns extended ( lf ) 200 ns 19* tiov2osh port input valid to osc1 (i/o in setup time) 0 ns 20* tior port output rise time standard ( f ) 10 40 ns extended ( lf ) 145 ns 21* tiof port output fall time standard ( f ) 10 40 ns extended ( lf ) 145 ns 22??* t inp int pin high or low time t cy n s 23??* t rbp rb7:rb4 change int high or low time t cy n s * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events, not related to any internal clock edges. note 1: measurements are taken in rc mode, where clko output is 4 x t osc . downloaded from: http:///
pic16f72 ds39597c-page 96 ? 2007 microchip technology inc. figure 14-6: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 14-7: brown-out reset timing table 14-3: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 14-3 for load conditions. v dd v bor 35 parameter no. symbol characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 sv dd = 5v, -40c to +85c 31* t wdt watchdog timer time-out period (no prescaler) 71 83 3m s v dd = 5v, -40c to +85c 32 t ost oscillation start-up timer period 1024 t osc t osc = osc1 period 33* t pwrt power-up timer period 28 72 132 ms v dd = 5v, -40c to +85c 34 t ioz i/o hi-impedance from mclr low or watchdog timer reset 2 . 1 s 35 t bor brown-out reset pulse width 100 sv dd v bor (d005) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance onl y and are not tested. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 97 pic16f72 figure 14-8: timer0 and timer1 external clock timings table 14-4: timer0 and timer1 external clock requirements param no. symbol characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5 t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 41* tt0l t0cki low pulse width no prescaler 0.5 t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 42* tt0p t0cki period no prescaler t cy + 40 ns with prescaler greater of: 20 or t cy + 40 n ns n = prescale value (2, 4, ..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5 t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 standard( f )1 5 n s extended( lf )2 5 n s asynchronous standard( f )3 0 n s extended( lf )5 0 n s 46* tt1l t1cki low time synchronous, prescaler = 1 0.5 t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 standard( f )1 5 n s extended( lf )2 5 n s asynchronous standard( f )3 0 n s extended( lf )5 0 n s 47* tt1p t1cki input period synchronous standard( f ) greater of: 30 or t cy + 40 n ns n = prescale value (1, 2, 4, 8) extended( lf ) greater of: 50 or t cy + 40 n n = prescale value (1, 2, 4, 8) asynchronous standard( f )6 0 n s extended( lf ) 100 ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc 200 khz 48 tckeztmr1 delay from external clock edge to timer increment 2 t osc 7 t osc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note: refer to figure 14-3 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1 downloaded from: http:///
pic16f72 ds39597c-page 98 ? 2007 microchip technology inc. figure 14-9: capture/compare/pwm timings (ccp1 ) table 14-5: capture/compare/pwm requirements (ccp1) note: refer to figure 14-3 for load conditions. rc2/ccp1 (capture mode) 50 51 52 53 54 rc2/ccp1 (compare or pwm mode) param no. symbol characteristic min typ? max units conditions 50* tccl ccp1 input low time no prescaler 0.5 t cy + 20 ns with prescaler standard( f )1 0 n s extended( lf )2 0n s 51* tcch ccp1 input high time no prescaler 0.5 t cy + 20 ns with prescaler standard( f )1 0 n s extended( lf )2 0n s 52* tccp ccp1 input period 3 t cy + 40 n ns n = prescale value (1,4 or 16) 53* tccr ccp1 output rise time standard( f ) 10 25 ns extended( lf ) 25 50 ns 54* tccf ccp1 output fall time standard( f ) 10 25 ns extended( lf ) 25 45 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 99 pic16f72 figure 14-10: spi master mo de timing (cke = 0, smp = 0) figure 14-11: spi master mo de timing (cke = 1, smp = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit6 - - - - - -1 msb in lsb in bit6 - - - -1 note: refer to figure 14-3 for load conditions. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit6 - - - - - -1 lsb in bit6 - - - -1 lsb note: refer to figure 14-3 for load conditions. downloaded from: http:///
pic16f72 ds39597c-page 100 ? 2007 microchip technology inc. figure 14-12: spi slave mode timing (cke = 0) figure 14-13: spi slave mode timing (cke = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 note: refer to figure 14-3 for load conditions. ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83 note: refer to figure 14-3 for load conditions. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 101 pic16f72 table 14-6: spi mode requirements figure 14-14: i 2 c bus start/stop bits timing param no. symbol characteristic min typ? max units conditions 70* tssl2sch, tssl2scl ss to sck or sck input t cy n s 71* tsch sck input high time (slave mode) t cy + 20 ns 72* tscl sck input low time (slave mode) t cy + 20 ns 73* tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ns 74* tsch2dil, tsc l2 di l hold time of sdi data input to sck edge 100 ns 75* tdor sdo data output rise time standard( f ) extended( lf ) 1025 2550 nsns 76* tdof sdo data output fall time 10 25 ns 77* tssh2doz ss to sdo output hi-impedance 10 50 ns 78* tscr sck output rise time (master mode) standard( f ) extended( lf ) 1025 2550 nsns 79* tscf sck output fall time (master mode) 10 25 ns 80* tsch2dov, tscl2dov sdo data output valid after sck edge standard( f ) extended( lf ) 50 145 nsns 81* tdov2sch, tdov2scl sdo data output setup to sck edge t cy n s 82* tssl2dov sdo data output valid after ss edge 50 ns 83* tsch2ssh, tscl2ssh ss after sck edge 1.5 t cy + 40 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note : refer to figure 14-3 for load conditions. 91 92 93 scl sda start condition stop condition 90 downloaded from: http:///
pic16f72 ds39597c-page 102 ? 2007 microchip technology inc. table 14-7: i 2 c bus start/stop bits requirements figure 14-15: i 2 c bus data timing param no. symbol characteristic min typ max units conditions 90* t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 91* t hd : sta start condition 100 khz mode 4000 ns after this period, the first clock pulse is generated hold time 400 khz mode 600 92* t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 * these parameters are characterized but not tested. note: refer to figure 14-3 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 103 pic16f72 table 14-8: i 2 c bus data requirements param no. symbol characteristic min max units conditions 100* t high clock high time 100 khz mode 4.0 s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 s device must operate at a minimum of 10 mhz ssp module 1.5 t cy 101* t low clock low time 100 khz mode 4.7 s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 s device must operate at a minimum of 10 mhz ssp module 1.5 t cy 102* t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 - 400 pf 103* t f sda and scl fall time 100 khz mode 300 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 - 400 pf 90* t su : sta start condition setup time 100 khz mode 4.7 s only relevant for repeated start condition 400 khz mode 0.6 s 91* t hd : sta start condition hold time 100 khz mode 4.0 s after this period, the first clock pulse is generated 400 khz mode 0.6 s 106* t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 s 107* t su : dat data input setup time 100 khz mode 250 ns (note 2) 400 khz mode 100 ns 92* t su : sto stop condition setup time 100 khz mode 4.7 s 400 khz mode 0.6 s 109* t aa output valid from clock 100 khz mode 3500 ns (note 1) 400 khz mode ns 110* t buf bus free time 100 khz mode 4.7 s time the bus must be free before a new transmission can start 400 khz mode 1.3 s c b bus capacitive loading 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement t su : dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released. downloaded from: http:///
pic16f72 ds39597c-page 104 ? 2007 microchip technology inc. table 14-9: a/d converter characteristics: pic16f72 (industrial) pic16lf72 (industrial) param no. sym characteristic min typ? max units conditions a01 n r resolution pic16f72 8 bits bit v ref = v dd = 5.12v, v ss v ain v ref pic16lf72 8 bits bit v ref = v dd = 2.2v a02 e abs total absolute error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a03 e il integral linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a04 e dl differential linearity error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a05 e fs full scale error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a06 e off offset error < 1 lsb v ref = v dd = 5.12v, v ss v ain v ref a10 monotonicity (note 3) guaranteed v ss v ain v ref a20 v ref reference voltage 2.5 2.2 v dd +0.3 v dd +0.3 vv -40c to +85c 0c to +85c a25 v ain analog input voltage v ss - 0.3 v ref + 0.3 v a30 z ain recommended impedance of analog voltage source 10.0 k a40 i ad a/d conversion current (v dd ) pic16f72 180 a average current consumption when a/d is on (note 1) . pic16lf72 90 a a50 i ref v ref input current (note 2) n/a 5 500 a a during v ain acquisition. during a/d conversion cycle. * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: v ref current is from the ra3 pin or the v dd pin, whichever is selected as a reference input. 3: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 105 pic16f72 figure 14-16: a/d conversion timing table 14-10: a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (t osc /2) (1) 7 6 5432 10 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 134 param no. sym characteristic min typ? max units conditions 130 t ad a/d clock period pic16f72 1.6 st osc based, v ref 3.0v pic16lf72 2.0 st osc based, 2.0v v ref 5.5v pic16f72 2.0 4.0 6.0 s a/d rc mode pic16lf72 3.0 6.0 9.0 s a/d rc mode 131 t cnv conversion time (not including s/h time) (note 1) 99t ad 132 t acq acquisition time 5* s the minimum time is the amplifier settling time. this may be used if the new input voltage has not changed by more than 1 lsb (i.e., 20.0 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). 134 t go q4 to a/d clock start t osc /2 if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. downloaded from: http:///
pic16f72 ds39597c-page 106 ? 2007 microchip technology inc. notes: downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 107 pic16f72 15.0 dc and ac characteristics graphs and tables typical represents the mean of the distribution at 25 c. maximum or minimum represents (mean + 3 ) or (mean - 3 ) respectively, where is a standard deviation, over the whole temperature range. figure 15-1: typical i dd vs. f osc over v dd (hs mode) figure 15-2: maximum i dd vs. f osc over v dd (hs mode) note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein a re not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified oper- ating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 0 1 2 3 4 5 6 4 6 8 10 12 14 16 18 20 f osc (m hz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) 0 1 2 3 4 5 6 7 8 4 6 8 10 12 14 16 18 20 f osc (m hz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) downloaded from: http:///
pic16f72 ds39597c-page 108 ? 2007 microchip technology inc. figure 15-3: typical i dd vs. f osc over v dd (xt mode) figure 15-4: maximum i dd vs. f osc over v dd (xt mode) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f osc (mhz) i dd (ma) 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 109 pic16f72 figure 15-5: typical i dd vs. f osc over v dd (lp mode) figure 15-6: maximum i dd vs. f osc over v dd (lp mode) 5540 15 10 2520 30 35 45 50 30 50 60 40 70 80 90 100 i dd ( a) f osc (khz) 3.5v 3.0v 2.0v 5.5v 5.0v 4.5v 4.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) 3020 30 50 60 40 70 80 90 100 i dd ( a) f osc (khz) 40 50 60 70 80 90 100 5.5v 5.0v 4.5v 4.0v 3.5v 3.0v 2.5v 2.0v downloaded from: http:///
pic16f72 ds39597c-page 110 ? 2007 microchip technology inc. figure 15-7: average f osc vs. v dd for various values of r (rc mode, c = 20 pf, 25 c) figure 15-8: average f osc vs. v dd for various values of r (rc mode, c = 100 pf, 25 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2 . 53 . 03 . 54 . 04 . 55 . 05 . 5 v dd (v) freq (mhz) 10 k 100 k operation above 4 mhz is not recomended 0.0 1.0 2.0 3.0 4.0 5.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) freq (mhz) 5.1 k 10 k 100 k operation above 4 mhz is not recomended downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 111 pic16f72 figure 15-9: average f osc vs. v dd for various values of r (rc mode, c = 300 pf, 25 c) figure 15-10: i pd vs. v dd (sleep mode, all peripherals disabled) 0 50 100 150 200 250 300 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) freq (khz) 3.3 k 5.1 k 10 k 100 k 0.01 0.1 1 10 100 2 . 02 . 53 . 03 . 54 . 04 . 55 . 05 . 5 v dd (v) i pd (ua) max 125c max 85c typ 25c typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) downloaded from: http:///
pic16f72 ds39597c-page 112 ? 2007 microchip technology inc. figure 15-11: i bor vs. v dd over temperature figure 15-12: typical and maximum i wdt vs. v dd over temperature 10 100 1,000 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v ) device in reset device in sleep indeterminant state max (125?c) typ (25?c) max (125?c) typ (25?c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) note: device current in reset depends on oscillator mode, frequency and circuit. i dd ( a) 0.1 1 10 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v ) max (125?c) typ (25?c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) i wdt ( a) downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 113 pic16f72 figure 15-13: typical, minimum and maximum wdt period vs. v dd (-40 c to +125 c) figure 15-14: average wdt period vs. v dd over temperature (-40 c to +125 c) 0 5 10 15 20 25 30 35 40 45 50 2 . 02 . 53 . 03 . 54 . 04 . 55 . 05 . 5 v dd (v) wdt period (ms) max (125c) typ (25c) min (-40c) 16f77 typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) 0 5 10 15 20 25 30 35 40 45 50 2 . 02 . 53 . 03 . 54 . 04 . 55 . 05 . 5 v dd (v) wdt period (ms) 125c 85c 25c -40c typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) downloaded from: http:///
pic16f72 ds39597c-page 114 ? 2007 microchip technology inc. figure 15-15: typical, minimum and maximum v oh vs. i oh (v dd = 5v, -40 c to +125 c) figure 15-16: typical, minimum and maximum v oh vs. i oh (v dd = 3v, -40 c to +125 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 5 10 15 20 25 i oh (-ma) v oh (v) max typ (25c) min typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 i oh (-ma) v oh (v) max typ (25c) min typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 115 pic16f72 figure 15-17: typical, minimum and maximum v ol vs. i ol (v dd = 5v, -40 c to +125 c) figure 15-18: typical, minimum and maximum v ol vs. i ol (v dd = 3v, -40 c to +125 c) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 5 10 15 20 25 i ol (-ma) v ol (v) max (125c) max (85c) typ (25c) min (-40c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 i ol (-ma) v ol (v) max (125c) max (85c) typ (25c) min (-40c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) downloaded from: http:///
pic16f72 ds39597c-page 116 ? 2007 microchip technology inc. figure 15-19: minimum and maximum v in vs. v dd , (ttl input, -40 c to +125 c) figure 15-20: minimum and maximum v in vs. v dd (st input, -40 c to +125 c) 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v th max (-40c) v th min (125c) v th typ (25c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v ih max (125c) v ih min (-40c) v il max (-40c) v il min (125c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean C 3 (-40c to +125c) downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 117 pic16f72 16.0 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it wil l be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead soic yywwnnn example xxxxxxxxxxxxxxxxx yywwnnn 28-lead pdip (skinny dip) example xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx 0717017 pic16f72-i/sp 0710017 pic16f72-i/so 28-lead ssop yywwnnn xxxxxxxxxxxx xxxxxxxxxxxx example 0720017 pic16f72 28-lead qfn example xxxxxxxx xxxxxxxx yywwnnn pic16f72 -i/ml 0710017 -i/ss 3 e 3 e 3 e 3 e downloaded from: http:///
pic16f72 ds39597c-page 118 ? 2007 microchip technology inc. 28-lead skinny plastic dual in-line (sp) C 300 mil body [spdip] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . significant characteristic. 3 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 28 pitch e .100 bsc top to seating plane a C C .200 molded package thickness a2 .120 .135 .150 base to seating plane a1 .015 C C shoulder to shoulder width e .290 .310 .335 molded package width e1 .240 .285 .295 overall length d 1.345 1.365 1.400 tip to seating plane l .110 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .050 .070 lower lead width b .014 .018 .022 overall row spacing eb C C .430 note 1 n 12 d e1 e b c e l a2 e b b1 a1 a 3 microchip technology drawing c04-070 b downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 119 pic16f72 28-lead plastic small outline (so) C wide, 7.50 mm body [soic] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . significant characteristic. 3 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millmeters dimension limits min nom max number of pins n 28 pitch e 1.27 bsc overall height a C C 2.65 molded package thickness a2 2.05 C C standoff a1 0.10 C 0.30 overall width e 10.30 bsc molded package width e1 7.50 bsc overall length d 17.90 bsc chamfer (optional) h 0.25 C 0.75 foot length l 0.40 C 1.27 footprint l1 1.40 ref foot angle top 0 C 8 lead thickness c 0.18 C 0.33 lead width b 0.31 C 0.51 mold draft angle top 5 C 15 mold draft angle bottom 5 C 15 c h h l l1 a2 a1 a note 1 12 3 b e e e1 d n microchip technology drawing c04-052 b downloaded from: http:///
pic16f72 ds39597c-page 120 ? 2007 microchip technology inc. 28-lead plastic shrink small outline (ss) C 5.30 mm body [ssop] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.20 mm per side. 3 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 28 pitch e 0.65 bsc overall height a C C 2.00 molded package thickness a2 1.65 1.75 1.85 standoff a1 0.05 C C overall width e 7.40 7.80 8.20 molded package width e1 5.00 5.30 5.60 overall length d 9.90 10.20 10.50 foot length l 0.55 0.75 0.95 footprint l1 1.25 ref lead thickness c 0.09 C 0.25 foot angle 0 4 8 lead width b 0.22 C 0.38 l l1 c a2 a1 a e e1 d n 1 2 note 1 b e microchip technology drawing c04-073 b downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 121 pic16f72 28-lead plastic quad flat, no lead package (ml) C 6x6 mm body [qfn] w ith 0.55 mm contact length n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . package is saw singulated. 3 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 28 pitch e 0.65 bsc overall height a 0.80 0.90 1.00 standoff a1 0.00 0.02 0.05 contact thickness a3 0.20 ref overall width e 6.00 bsc exposed pad width e2 3.65 3.70 4.20 overall length d 6.00 bsc exposed pad length d2 3.65 3.70 4.20 contact width b 0.23 0.30 0.35 contact length l 0.50 0.55 0.70 contact-to-exposed pad k 0.20 C C d exposed d2 e b k e2 e l n note 1 1 2 2 1 n a a1 a 3 top vie bottom vie pad microchip technology drawing c04-105 b downloaded from: http:///
pic16f72 ds39597c-page 122 ? 2007 microchip technology inc. notes: downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 123 pic16f72 appendix a: revision history revision a (april 2002) this is a new data sheet. however, this device is sim- ilar to the pic16c72 device found in the pic16c7x data sheet (ds30390), the pic16c72a data sheet (ds35008) or the pic16f872 device (ds30221). revision b (may 2002) final data sheet. includes device characterization data. minor typographic revisions throughout. revision c (january 2007) this revision includes updates to the packaging diagrams. appendix b: convers ion considerations considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in table b-1. table b-1: conversion considerations characteristic pic16c72/72a pic16f872 pic16f72 pins 28 28 28 timers 3 3 3 interrupts 8 10 8 communication basic ssp/ssp (spi, i 2 c slave) mssp (spi, i 2 c master/slave) ssp (spi, i 2 c slave) frequency 20 mhz 20 mhz 20 mhz a/d 8-bit, 5 channels 10-bit, 5 channels 8-bit, 5 channels ccp 1 1 1 program memory 2k eprom 2k flash (1,000 e/w cycles) 2k flash (1000 e/w cycles) ram 128 bytes 128 bytes 128 bytes eeprom data none 64 bytes none other in-circuit debugger, low voltage programming downloaded from: http:///
pic16f72 ds39597c-page 124 ? 2007 microchip technology inc. notes: downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 125 pic16f72 index a a/d acquisition requirements .......................................... . 56 adcon0 register....................................................... 53 adcon1 register....................................................... 53 adif bit ....................................................................... 54 adres register ......................................................... 53 analog-to-digital converter......................................... 53 associated registers .................................................. 57 configuring analog port pins...................................... 56 configuring the interrupt ............................................. 54 configuring the module........................................... .... 54 conversion clock........................................................ 56 conversions ................................................................ 56 converter characteristics ......................................... 104 effects of a reset ..................................................... 57 internal sampling switch (rss) impedance ................ 56 operation during sleep ............................................ 57 source impedance.............................................. ........ 56 use of the the ccp trigger......................................... 57 absolute maximum ratings ................................................ 87 ack ..................................................................................... 49 adcon0 go/done bit ...................................................... 54 adres register ............................................................. 9, 54 application notes an546 (using the analog-to-digital converter) .......... 53 an552 (implementing wake-up on key strokes using pic16f7x) ............................... 23 an556 (implementing a table read).......................... 19 an578 (use of the ssp module in the i 2 c multi-master environment)............................... 43 an607 (power-up trouble shooting) .......................... 64 assembler mpasm assembler ..................................................... 81 b bf ....................................................................................... 44 block diagrams a/d .............................................................................. 55 analog input model .............................................. ....... 55 capture mode operation ............................................ 38 compare mode operation .......................................... 39 in-circuit serial programming connections................ 72 interrupt logic ............................................................. 68 on-chip reset circuit ................................................. 63 pic16f72...................................................................... 5 portc ....................................................................... 25 pwm ........................................................................... 41 ra3:ra0 and ra5 port pins ...................................... 21 ra4/t0cki pin............................................................ 21 rb3:rb0 port pins ..................................................... 23 rb7:rb4 port pins ..................................................... 23 recommended mclr circuit ..................................... 63 ssp in i 2 c mode......................................................... 48 ssp in spi mode ........................................................ 46 timer0/wdt prescaler................................................ 29 timer1 ......................................................................... 32 timer2 ......................................................................... 35 watchdog timer (wdt) ........................................ ...... 70 bor. see brown-out reset brown-out reset (bor) .................................... 59, 62, 65 , 66 buffer full status bit, bf ............................................... ...... 44 c capture/compare/pwm ..................................................... 37 associated registers with pwm and timer2.............. 42 associated registers, capture, compare and timer1................................................ ............. 40 capture ccp1if............................................................... 38 ccpr1 ............................................................... 38 ccpr1h:ccpr1l.............................................. 38 capture mode............................................................. 38 ccp mode timer resources...................................... 37 ccp pin configuration ......................................... 38, 39 ccp prescaler............................................................ 38 ccpr1l register ....................................................... 37 compare mode ........................................................... 39 pwm mode................................................................. 41 pwm, example frequencies/resolutions .................. 42 software interrupt ....................................................... 38 software interrupt mode ............................................. 39 special event trigger and a/d conversions .............. 39 special event trigger output of ccp1 ....................... 39 timer1 mode selection........................................ . 38, 39 ccpr1h register............................................................... 37 ccpxm0 bit......................................................................... 37 ccpxm1 bit......................................................................... 37 ccpxm2 bit......................................................................... 37 ccpxm3 bit......................................................................... 37 ccpxx bit ........................................................................... 37 ccpxy bit ........................................................................... 37 cke .................................................................................... 44 ckp .................................................................................... 45 clock polarity select bit, ckp............................................. 45 code examples changing between capture prescalers ..................... 38 flash program read................................................ 28 indirect addressing..................................................... 19 initializing porta....................................................... 21 initializing portb ...................................................... 23 initializing portc ...................................................... 25 saving status, w and pclath registers in ram................................................... 69 code protection ............................................... ............. 59, 72 configuration bits ....................................................... ........ 59 configuration word........................................................... .. 60 conversion considerations............................................... 123 dd/a ...................................................................................... 44 data memory general purpose register file ..................................... 7 special function registers........................................... 9 data/address bit, d/a ......................................................... 44 dc and ac characteristics graphs and tables ............................................... .... 107 dc characteristics.............................................................. 89 development support ......................................................... 81 device overview................................................................... 5 direct addressing ............................................................. .. 20 e electrical characteristics .................................................... 87 errata .................................................................................... 3 downloaded from: http:///
pic16f72 ds39597c-page 126 ? 2007 microchip technology inc. f flash program memory associated registers .................................................. 28 operation during code protect................................... 28 reading.................................................. ..................... 28 fsr register................................................................... 9, 10 i i/o ports .............................................................................. 21 porta ........................................................................ 21 portb........................................................................ 23 portc........................................................................ 25 i 2 c associated registers .................................................. 51 master mode ............................................................... 51 mode selection ................................................ ........... 48 multi-master mode ...................................................... 51 scl and sda pins ................................................ ...... 48 slave mode ................................................................. 48 icepic in-circuit emulator ................................................. 82 id locations ........................................................................ 72 in-circuit serial programming (icsp) ................................. 72 indf register ..................................................................... 10 indirect addressing ............................................................. 20 fsr register .............................................................. 19 indf register ............................................................. 19 instruction format ............................................................... 73 instruction set .......................................................... ........... 73 addlw ....................................................................... 75 addwf ....................................................................... 75 andlw ....................................................................... 75 andwf ....................................................................... 75 bcf ............................................................................. 75 bsf ............................................................................. 75 btfsc ........................................................................ 76 btfss ........................................................................ 76 call ........................................................................... 76 clrf........................................................................... 76 clrw.......................................................................... 76 clrwdt..................................................................... 76 comf ......................................................................... 77 decf .......................................................................... 77 decfsz...................................................................... 77 goto.......................................................................... 77 incf............................................................................ 77 incfsz ....................................................................... 77 iorlw......................................................................... 78 iorwf ........................................................................ 78 movf.......................................................................... 78 movlw....................................................................... 78 movwf ...................................................................... 78 nop ............................................................................ 78 retfie ....................................................................... 79 retlw........................................................................ 79 return ..................................................................... 79 rlf ............................................................................. 79 rrf............................................................................. 79 sleep ........................................................................ 79 sublw........................................................................ 80 subwf ....................................................................... 80 summary table ........................................................... 74 swapf ....................................................................... 80 xorlw ....................................................................... 80 xorwf....................................................................... 80 int interrupt (rb0/int). see interrupt sources intcon register gie bit......................................................................... 14 inte bit....................................................................... 14 intf bit ....................................................................... 14 rbif bit....................................................................... 14 tmr0ie bit.................................................................. 14 internal sampling switch (rss) impedance........................ 56 interrupt sources .......................................................... 59, 68 rb0/int pin, external................................................. 69 tmr0 overflow........................................................... 69 interrupts rb7:rb4 port change............................................. ... 23 synchronous serial port interrupt............................... 16 interrupts, context saving during....................................... 69 interrupts, enable bits global interrupt enable (gie bit) .......................... 14, 68 interrupt-on-change (rb7:rb4) enable (rbie bit) ............................................. ...... 69 rb0/int enable (inte bit) ......................................... 14 tmr0 overflow enable (tmr0ie bit) ......................... 14 interrupts, flag bits interrupt-on-change (rb7:rb4) flag (rbif bit) ............................................................... 14 interrupt-on-change (rb7:rb4) flag (rbif bit) ......................................................... 14, 69 rb0/int flag (intf bit).............................................. 14 tmr0 overflow flag (tmr0if bit).............................. 69 kk ee l oq evaluation and programming tools ...................... 84 l loading of pc ............................................... ...................... 18 m master clear (mclr ) mclr reset, normal operation..................... 62, 65, 66 mclr reset, sleep...................................... 62, 65, 66 operation and esd protection ................................... 63 memory data memory ................................................................ 7 program memory .......................................................... 7 mplab c17 and mplab c18 c compilers ....................... 81 mplab icd in-circuit debugger ........................................ 83 mplab ice high performance universal in-circuit emulator with mplab ide ............................ 82 mplab integrated development environment software .................................................. 81 mplink object linker/mplib object librarian .................. 82 o on-line support ............................................... ................ 131 opcode field descriptions............................................... 73 option_reg register intedg bit ................................................................. 13 ps2:ps0 bits............................................................... 13 psa bit........................................................................ 13 rbpu bit ..................................................................... 13 t0cs bit...................................................................... 13 t0se bit ...................................................................... 13 downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 127 pic16f72 oscillator configuration................................................. 59, 61 crystal oscillator/ceramic res onators ....................... 61 hs ......................................................................... 61, 65 lp.......................................................................... 61, 65 rc................................................................... 61, 62, 65 xt ......................................................................... 61, 65 oscillator, wdt ................................................................... 70 p p.......................................................................................... 44 package marking information ..................................... ...... 117 pcfg0 bit ........................................................................... 54 pcfg1 bit ........................................................................... 54 pcfg2 bit ........................................................................... 54 pcl register............................................................. 9, 10, 18 pclath register ..................................................... 9, 10, 18 pcon register ................................................................... 64 por bit ....................................................................... 17 picdem 1 low cost pic demonstration board.................................................... 83 picdem 17 demonstration board ...................................... 84 picdem 2 low cost pic16cxx demonstration board.................................................... 83 picdem 3 low cost pic16cxxx demonstration board.................................................... 84 picstart plus entry level development programmer ........................................... 83 pin functions mclr /v pp ..................................................................... 6 osc1/clki ................................................................... 6 osc2/clko ................................................................. 6 ra0/an0 ....................................................................... 6 ra1/an1 ....................................................................... 6 ra2/an2 ....................................................................... 6 ra3/an3/v ref .............................................................. 6 ra4/t0cki.................................................................... 6 ra5/an4/ss ................................................................. 6 rb0/int ........................................................................ 6 rb1 ............................................................................... 6 rb2 ............................................................................... 6 rb3 ............................................................................... 6 rb4 ............................................................................... 6 rb5 ............................................................................... 6 rb6/pgc ...................................................................... 6 rb7/pgd ...................................................................... 6 rc0/t1oso/t1cki ...................................................... 6 rc1/t1osi ................................................................... 6 rc2/ccp1 .................................................................... 6 rc3/sck/scl .............................................................. 6 rc4/sdi/sda ............................................................... 6 rc5/sdo ...................................................................... 6 rc6............................................................................... 6 rc7............................................................................... 6 v dd ............................................................................... 6 v ss ................................................................................ 6 pinout descriptions pic16f72...................................................................... 6 pop .................................................................................... 19 por. see power-on reset porta associated registers .................................................. 22 functions .................................................................... 22 porta register ................................................................... 9 portb associated registers.................................................. 24 functions .................................................................... 24 pull-up enable (rbpu bit) .......................................... 13 rb0/int edge select (intedg bit)............................ 13 rb0/int pin, external ................................................ 69 rb7:rb4 interrupt-on-change flag (rbif bit)........... 14 rb7:rb4 interrupt-on-change ................................... 69 rb7:rb4 interrupt-on-change enable (rbie bit) ............................................................... 69 rb7:rb4 interrupt-on-change flag (rbif bit) ......................................................... 14, 69 portb register ................................................................... 9 portc associated registers.................................................. 26 functions .................................................................... 26 portc register................................................................... 9 postscaler, wdt assignment (psa bit) ................................................. 13 rate select (ps2:ps0 bits) ........................................ 13 power-down mode. see sleep power-on reset (por)............................... 59, 62, 64, 65, 66 brown-out reset (bor).............................................. 64 oscillator start-up timer (ost) ............................ 59, 64 por status (por bit)................................................. 17 power control/status register (pcon)...................... 64 power-down (pd bit) .................................................. 62 power-up timer (pwrt) ...................................... 59, 64 time-out (to bit) .................................................. 12, 62 time-out sequence ............................................. ....... 64 pr2 register ...................................................................... 35 prescaler, timer0 assignment (psa bit) ................................................. 13 rate select (ps2:ps0 bits) ........................................ 13 pro mate ii universal device programmer ..................... 83 product identification system ........................................ ... 133 program counter reset conditions............................................. ......... 65 program memory paging ........................................................................ 19 program memory map and stack ......................................... 7 program verification ......................................................... .. 72 push.................................................................................. 19 rr/w ..................................................................................... 44 r/w bit................................................................................ 49 rbif bit............................................................................... 23 read/write bit information, r/w ......................................... 44 reader response................................................. ............ 132 reading program memory................................................ .. 27 pmadr....................................................................... 27 pmcon1 register...................................................... 27 receive overflow indicator bit, sspov.............................. 45 register file map.............................................................. .... 8 downloaded from: http:///
pic16f72 ds39597c-page 128 ? 2007 microchip technology inc. registers ............................................................................. 36 adcon0 (a/d control 0) ............................................ 53 adcon1 (a/d control 1) ............................................ 54 ccpcon1 (capture/compare/pwm control 1) ......... 37 initialization conditions (table) .................................... 66 intcon (interrupt control) ......................................... 14 option ...................................................................... 13 pcon (power control) ............................................... 17 pie1 (peripheral interrupt enable 1) ........................... 15 pir1 (peripheral interrupt flag 1) ............................... 16 pmcon1 (program memory control 1) ...................... 27 sspcon (sync serial port control) ........................... 45 sspstat (synchronous serial port status) ............... 44 status ...................................................................... 12 summary....................................................................... 9 t1con (timer1 control)............................................. 31 reset .......................................................................... 59, 62 brown-out reset (bor). see brown-out reset (bor) mclr reset. see mclr power-on reset (por). see power-on reset (por) reset conditions for all registers............................ 66 reset conditions for pcon register ....................... 65 reset conditions for program counter .................... 65 reset conditions for status register .................... 65 wdt reset. see watchdog timer (wdt) revision history ................................................................ 1 23 rp0, rp1 bit ......................................................................... 7 s s.......................................................................................... 44 sales and support.................................................. ........... 133 slave mode scl ............................................................................. 48 sda............................................................................. 48 sleep..................................................................... 59, 62, 71 smp .................................................................................... 44 software simulator (mplab sim)....................................... 82 special event trigger.......................................................... 57 special features of the cpu............................................... 59 special function registers pmadrh .................................................................... 27 pmadrl ..................................................................... 27 pmcon1..................................................................... 27 pmdath ..................................................................... 27 pmdatl...................................................................... 27 spi associated registers .................................................. 46 spi clock edge select bit, cke......................................... . 44 spi data input sample phase select bit, smp................... 44 spi mode serial clock................................................................. 43 serial data in .............................................................. 43 serial data out............................................................ 43 slave select ................................................................ 43 ssp ack ............................................................................. 48 addressing .................................................................. 48 bf bit........................................................................... 48 i 2 c mode operation ................................................ .... 48 r/w bit ........................................................................ 49 reception .................................................................... 49 scl clock input ................................................. ......... 48 sspov bit................................................................... 48 transmission............................................................... 49 sspadd register............................................................... 10 sspen................................................................................ 45 sspif ................................................................................. 16 sspm3:sspm0 .................................................................. 45 sspov ............................................................................... 45 sspstat register ............................................................. 10 stack................................................................................... 19 overflows.................................................................... 19 underflow ................................................ ................... 19 start bit, s....................................................................... 44 status register dc bit.......................................................................... 12 irp bit ......................................................................... 12 pd bit.......................................................................... 62 to bit .................................................................... 12, 62 stop bit, p......................................................................... 44 synchronous serial port (ssp) ........................................ .. 43 overview..................................................................... 43 spi mode .................................................................... 43 synchronous serial port enable bit, sspen...................... 45 synchronous serial port interrupt...................................... . 16 synchronous serial port mode select bits, sspm3:sspm0 ............................................................ 45 t t2ckps0 bit ....................................................................... 36 t2ckps1 bit ....................................................................... 36 t2con (timer2 control) .................................................... 36 t ad ...................................................................................... 56 timer0................................................................................. 29 clock source edge select (t0se bit)......................... 13 clock source select (t0cs bit) .................................. 1 3 external clock............................................................. 30 interrupt ...................................................................... 29 operation .................................................................... 29 overflow enable (tmr0ie bit) .................................... 14 overflow flag (tmr0if bit) ........................................ 69 overflow interrupt ....................................................... 69 prescaler .................................................................... 30 t0cki ......................................................................... 30 timer1 associated registers .................................................. 34 asynchronous counter mode ..................................... 33 capacitor selection..................................................... 33 counter operation .............................................. ........ 32 interrupt ...................................................................... 33 operation in timer mode ............................................ 32 oscillator..................................................................... 33 prescaler .................................................................... 34 resetting tmr1h, tmr1l register pair.................... 34 resetting using a ccp trigger output....................... 33 synchronized counter mode ...................................... 32 timer2................................................................................. 35 interrupt ...................................................................... 35 operation .................................................................... 35 output ......................................................................... 35 prescaler, postscaler .................................................. 35 downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 129 pic16f72 timing diagrams a/d conversion......................................................... 105 brown-out reset ......................................................... 96 capture/compare/pwm (ccp1)................................. 98 clko and i/o .............................................. ............... 95 external clock............................................................. 94 i 2 c bus data ............................................................. 102 i 2 c bus start/stop bits........................................ 101 i 2 c reception (7-bit address) ..................................... 50 i 2 c transmission (7-bit address) ................................ 50 reset, watchdog timer, oscillator start-up timer and power-up timer........................................... .... 96 slow rise time (mclr tied to v dd through rc network)........................................................... 68 spi master mode ........................................................ 47 spi master mode (cke = 0, smp = 0) ....................... 99 spi master mode (cke = 1, smp = 1) ....................... 99 spi slave mode (cke = 0) ................................. 47, 100 spi slave mode (cke = 1) ................................. 47, 100 time-out sequence on power-up (mclr tied to v dd through pull-up resistor)............................... 67 time-out sequence on power-up (mclr tied to v dd through rc network): case 1 ....................... 67 time-out sequence on power-up (mclr tied to v dd through rc network): case 2 ....................... 67 timer0 and timer1 external clock.............................. 97 wake-up from sleep through interrupt ..................... 72 timing parameter symbology............................................. 93 tmr1h register ................................................................... 9 tmr1l register.................................................................... 9 tmr2 register...................................................................... 9 tmr2on bit ........................................................................ 36 toutps0 bit....................................................................... 36 toutps1 bit....................................................................... 36 toutps2 bit....................................................................... 36 toutps3 bit....................................................................... 36 trisa register ............................................................. 10, 21 trisb register ............................................................. 10, 23 trisc register............................................................. 10, 25 u ua....................................................................................... 44 update address bit, ua ............................................ .......... 44 w wake-up from sleep................................................... 59, 71 interrupts .............................................................. 65, 66 mclr reset ............................................................... 66 wdt reset ................................................................. 66 watchdog timer (wdt)......................................... ....... 59, 70 associated registers.................................................. 70 enable (wdten bit) ............................................... .... 70 postscaler. see postscaler, wdt programming considerations ..................................... 70 rc oscillator .............................................................. 70 time-out period .......................................................... 70 wdt reset, normal operation....................... 62, 65, 66 wdt reset, sleep ....................................... 62, 65, 66 wcol ................................................................................. 45 write collision detect bit, wcol........................................ 45 www, on-line support .................... ................................... 3 downloaded from: http:///
pic16f72 ds39597c-page 130 ? 2007 microchip technology inc. notes: downloaded from: http:///
? 2005 microchip technology inc. advance information ds00000a-page 131 dstemp the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software ? general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com downloaded from: http:///
dstemp ds00000a-page 132 advance information ? 2005 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in wh ich our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this docume nt. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds00000a dstemp 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? downloaded from: http:///
? 2007 microchip technology inc. ds39597c-page 133 pic16f72 product identification system to order or obtain information, e.g. , on pricing or delivery, refer to the factory or the listed sales office. * jw devices are uv erasable and can be program med to any device configuration. jw devices meet the electrical requirement of each oscillator type. part no. x /xx xxx pattern package temperature range device device pic16f72: standard v dd range pic16f72t: (tape and reel) pic16lf72: extended v dd range temperature range - = 0c to +70c i = -40c to +85c package so = soic ss = ssop ml = qfn p=p d i p pattern qtp, sqtp, rom code (factory specified) or special requirements. blank for otp and windowed devices. examples: a) pic16f72-04i/so = industrial temp., soic package, normal v dd limits b) pic16lf72-20i/ss = industrial temp., ssop package, extended v dd limits c) pic16f72-20i/ml = industrial temp., qfn package, normal v dd limits downloaded from: http:///
ds39597c-page 134 ? 2007 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway habour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7250 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - gumi tel: 82-54-473-4301 fax: 82-54-473-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - penang tel: 60-4-646-8870 fax: 60-4-646-5086 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 12/08/06 downloaded from: http:///

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